设计验证工程师
Design Verification Engineer
关于团队：
OpenAI的硬件部门开发适用于先进AI工作负载独特需求的AI原生芯片和系统级解决方案。在Jalapeño等工作的基础上，该团队正在开发下一代AI原生芯片和高度集成的系统，以支持前沿模型的下一次迭代。通过协同设计芯片、系统、工具和方法，该团队帮助为OpenAI的超算平台交付更快、更高效且可投入生产的硬件。
关于职位：
OpenAI正在开发定制芯片，以支持下一代前沿AI模型。我们正在寻找有经验的设计验证（DV）工程师，以确保我们最先进的ML加速器的功能正确性和稳健设计。你将在验证复杂硬件系统方面发挥关键作用——从单个IP模块到子系统和完整SoC，与架构、RTL、软件和系统团队紧密合作，实现大规模可靠芯片的交付。
在此职位中，你将负责：
- 负责一个或多个模块的验证：定制IP模块、子系统（计算、互连、内存等）或全芯片SoC级别的功能。
- 根据架构和微架构规格定义验证计划。
- 使用SystemVerilog/UVM或同等方法开发约束随机、定向和系统级测试平台。
- 构建和维护激励生成器、检查器、监视器和评分板，以确保高覆盖率和正确性。
- 推动缺陷分类、根本原因分析，并与设计团队密切合作解决问题。
- 为模块级和顶层环境的回归基础设施、覆盖率分析和关闭做出贡献。
如果你具备以下条件，可能会在这个职位上表现出色：
- 电子工程、计算机工程或计算机科学学士/硕士及以上学历，具有3年以上硬件验证经验。
- 在工业标准流程中成功验证过复杂IP或SoC设计。
- 精通SystemVerilog、UVM以及常见的仿真和调试工具（例如VCS、Questa、Verdi）。
- 对计算机体系结构概念、内存和缓存系统、一致性、互连和/或ML计算原语有深入了解。
- 熟悉性能建模、形式化验证或仿真者优先。
- 有在快节奏、跨学科团队中工作的经验，对构建可靠硬件充满热情。
查看英文原文
About the Team:
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.
In this role you will:
- Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
- Define verification plans based on architecture and microarchitecture specs.
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
- Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
- Drive bug triage, root cause analysis, and work closely with design teams on resolution.
- Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.
You might thrive in this role if you have:
- BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
- Proven success verifying complex IP or SoC designs in industry-standard flows
- Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
- Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
- Familiarity with performance modeling, formal verification, or emulation is a plus.
- Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement https://cdn.openai.com/policies/eeo-policy-statement.pdf.
Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
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At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.