高级嵌入式软件工程师(C++)- 硬件安全
Senior Embedded Software Engineer (C++) - Hardware Safety
Latitude AI(lat.ai)正在构建福特自动驾驶路线图的未来,让每个人的出行更安全、更轻松、更愉快。将这一愿景规模化,我们自主研发的全功能无手自动驾驶平台将于2027年首次搭载在全新福特Fathom车型上。
加入Latitude团队,你将与机器学习和机器人技术、云平台、地图、传感器和计算系统、测试运营、系统和安全工程等领域的专家共同工作——所有这些人都致力于为数百万客户重新定义人与车辆之间的关系。
作为福特汽车公司的子公司,我们独立运作,以科技初创企业的速度开发自动驾驶技术。Latitude总部位于匹兹堡,密歇根州迪尔伯恩和加利福尼亚州帕洛阿尔托设有工程中心。
了解我们的团队:
嵌入式软件团队负责开发对公司整体发展至关重要的基础平台软件。硬件安全与电源系统组专注于在故障状态、电源转换和热事件期间协调安全系统行为的实时固件。
我们为TDA4(Jacinto 7)嵌入式目标设备开发基于FreeRTOS和SafeRTOS的驱动程序、状态机和诊断框架,用于电源管理、温度监控、电压监控和硬件看门狗系统。项目通常需要与硬件团队(PMIC供应商、SoC架构师)、安全工程师(符合ISO 26262标准)以及公司内部系统集成团队进行深入协作。
你将负责:
- 负责硬件安全和电源管理系统端到端架构:设计安全状态策略,跨多个核心和PMIC的电源时序,温度调节,以及看门狗协调。你的设计必须满足ASIL-B/C安全目标
- 直接从数据手册和TDA4功能安全手册中实现安全关键集成电路(PMIC、电压监控器、温度监测器)的底层驱动程序和固件。这些驱动程序运行在裸机和FreeRTOS上;它们必须无错误且可测试
- 领导硬件-软件安全诊断框架的开发——将TI安全诊断库(LBIST、PBIST、ECC、DCC、ESM)集成到固件中;确保诊断覆盖率映射到ISO 26262硬件故障指标;指导工程师进行覆盖率可追溯性
- 对所有硬件安全模块进行深入的代码审查。确保PR简单、无错误、
查看英文原文
Latitude AI (lat.ai) is building the future of Ford’s autonomy roadmap to make travel safer, less stressful, and more enjoyable for everyone. Bringing this vision to scale, our fully in-house developed hands-free ADAS platform will debut on the all-new Ford Fathom in 2027.
When you join the Latitude team, you’ll work alongside leading experts across machine learning and robotics, cloud platforms, mapping, sensors and compute systems, test operations, systems and safety engineering – all dedicated to redefining the relationship between people and their vehicles for millions of customers.
As a Ford Motor Company subsidiary, we operate independently to develop automated driving technology at the speed of a technology startup. Latitude is headquartered in Pittsburgh with engineering centers in Dearborn, Mich., and Palo Alto, Calif.
Meet the team:
The Embedded Software team develops foundational platform software critical to development across the company. The Hardware Safety & Power Systems group specializes in the real-time firmware that orchestrates safe system behavior during fault conditions, power transitions, and thermal events.
We develop FreeRTOS and SafeRTOS-based drivers, state machines, and diagnostic frameworks for power management, thermal monitoring, voltage supervision, and hardware watchdog systems on TDA4 (Jacinto 7) embedded targets. Projects often require deep collaboration with hardware teams (PMIC vendors, SoC architects), safety engineers (ISO 26262 compliance), and system integration teams across the company.
What you’ll do:
- Own the end-to-end architecture of hardware safety and power management systems: design safe-state strategies, power sequencing across multiple cores and PMICs, thermal throttling, and watchdog orchestration. Your designs must meet ASIL-B/C safety goals
- Implement low-level drivers and firmware for safety-critical integrated circuits (PMIC, voltage supervisor, thermal monitor) directly from datasheets and the TDA4 Functional Safety Manual. These drivers run on bare metal and FreeRTOS; they must be bug-free and testable
- Lead the development of hardware-software safety diagnostic frameworks — integrate TI Safety Diagnostic Library (LBIST, PBIST, ECC, DCC, ESM) into the firmware; ensure diagnostic coverage maps to ISO 26262 hardware fault metrics; mentor engineers on coverage traceability
- Consistently perform deep-dive code reviews across all hardware safety modules. Ensure PRs are simple, bug-free, and adhere to unified architectural vision (clean driver interfaces, consistent error handling, testable design patterns). Root out assumptions that could lead to latent ASIL-rated failures
- Serve as the SME for hardware-firmware-safety interfaces. Navigate ambiguity in hardware requirements (PMIC sequencing, watchdog timing, thermal limits, voltage thresholds). Mediate disagreements in technical approach through evidence-based influence and clear understanding of safety constraints
- Mentor engineers on embedded safety patterns — code review discipline, hardware driver architecture, RTOS integration, ISO 26262 traceability, and functional safety reasoning. Build capability across the team
What you'll need to succeed:
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, Robotics or a related field and 4+ years of relevant experience (or Master's degree and 2+ years of relevant experience, or PhD)
- Experience in embedded C/C++ with deep understanding of advanced language features, design paradigms, and embedded constraints (no exceptions, no RTTI, careful memory management). Proven ability to design clean abstractions and interface-based code for testability
- Proven expertise in ARM-based SoC architectures, specifically ARM Cortex-R5F: memory-mapped I/O, interrupt controllers (VIM), MPU configuration, cache behavior, and memory barriers. Experience debugging at the register level using datasheets
- Direct experience configuring MPUs and hardware-level firewalls to enforce spatial and temporal isolation in multi-core, safety-critical environments
- Experience building or significantly refactoring Hardware Abstraction Layers (HAL) to support multiple hardware targets, RTOS environments, or variant configurations. Understands the role of HAL in isolating driver complexity and enabling testing
- Ability to root-cause complex system failures — power sequencing hangs, missed watchdog feeds, thermal throttle race conditions, interrupt latency issues — involving shared memory, RTOS task scheduling, and hardware peripherals without supervision
- Ability to see potential pitfalls in low-level designs (e.g., power rail ordering dependencies, watchdog timeout misconfiguration, voltage threshold hysteresis). Can express designs in sufficient detail (state diagrams, timing requirements, register-level sequences) for rapid, correct implementation
- Expert-level use of embedded debugging tools (JTAG, on-target debugging, logic analyzers) to verify low-level hardware-software interactions and timing-critical behavior
- Deep understanding of Real-Time Operating Systems — FreeRTOS and/or SafeRTOS: task lifecycle, inter-task synchronization, interrupt handling, timing constraints, and periodic task patterns. Comfortable reasoning about task preemption, priority inversion, and stack requirements
- Direct experience developing drivers for safety-critical integrated circuits (PMIC, voltage supervisor, thermal sensor, or equivalent) from datasheet: SPI/I2C protocol implementation, register-level configuration, fault handling, and diagnostic integration
- Foundational knowledge of ISO 26262 ASIL-B/C functional safety concepts — safe-state strategies, diagnostic coverage, hardware/software fault tolerance allocation, and traceability. Ability to map code behavior to safety requirements without constant guidance
Nice to have:
- Direct experience with TDA4 / J784S4 (Jacinto 7) or other TI automotive SoCs — familiarity with TI PSDK, SDL (Safety Diagnostic Library), register maps, and peripheral architecture significantly accelerates ramp-up
- Expertise in Linux-based embedded software development including gtests, Python scripting, Bazel build system, and Docker containerization for embedded CI/CD
- Prior involvement in ISO 26262 functional safety audits or certification — experience with Jama requirements traceability, FMEA/HARA, and safety case argumentation
- Experience with hardware diagnostic frameworks — LBIST (Logic BIST), PBIST (Programmable BIST), ECC integration, or other ISO 26262 diagnostic mechanisms
- Proficiency with advanced embedded debugging tools — Tracealyzer for RTOS visualization, logic analyzers for protocol decoding, or in-circuit emulators
- Prior automotive or safety-critical domain experience — body control, powertrain, medical devices, industrial control, or aerospace/defense
What we offer you:
- Competitive compensation packages
- High-quality individual and family medical, dental, and vision insurance
- Health savings account with available employer match
- Employer-matched 401(k) retirement plan with immediate vesting
- Employer-paid group term life insurance and the option to elect voluntary life insurance
- Paid parental leave
- Paid medical leave
- Unlimited vacation
- 15 paid holidays
- Daily lunches, snacks, and beverages available in all office locations
- Pre-tax spending accounts for healthcare and dependent care expenses
- Pre-tax commuter benefits
- Monthly wellness stipend
- Adoption/Surrogacy support program
- Backup child and elder care program
- Professional development reimbursement
- Employee assistance program
- Discounted programs that include legal services, identity theft protection, pet insurance, and more
- Company and team bonding outlets: employee resource groups, quarterly team activity stipend, and wellness initiatives
Learn more about Latitude’s team, mission and career opportunities at lat.ai!
The expected base salary range for this full-time position in California is $160,000 - $240,000 USD. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Latitude employees are also eligible to participate in Latitude’s annual bonus programs, equity compensation, and generous Company benefits program, subject to eligibility requirements.
Candidates for positions with Latitude AI must be legally authorized to work in the United States on a permanent basis. Verification of employment eligibility will be required at the time of hire. Visa sponsorship is available for this position.
#LI-CG1
We are an Equal Opportunity Employer committed to a culturally diverse workforce. All qualified applicants will receive consideration for employment without regard to race, religion, color, age, sex, national origin, sexual orientation, gender identity, disability status or protected veteran status.