高级信号完整性工程师
Senior Signal Integrity Engineer
职位描述
高级信号完整性工程师
关于我们：
DriveNets处于高速电子创新解决方案开发的最前沿。我们先进的技术服务于下一代网络和通信，包括以太网路由器和高性能平台，用于最苛刻的应用。我们致力于解决复杂挑战，并推动信号和电源完整性的可能性边界。
职位描述：
我们正在寻找一位经验丰富的高级信号完整性工程师加入我们的硬件工程团队。该职位专注于确保高速接口（包括以太网、PCIe、DDR5和其他下一代技术）的最优信号完整性。作为团队成员，您将负责执行信号完整性分析、开发信号完整性模型，并确保高速SERDES I/O的电气合规性。
职责：
- 对112Gbps以太网、PCIe Gen5和DDR5接口等高速接口进行信号完整性分析和仿真。
- 开发并实施PCB设计的信号完整性指南，确保高性能和低损耗信号路径。
- 分析和解决与高速接口相关的信号完整性问题，包括反射、串扰和电源分配网络（PDN）问题。
- 与PCB布局工程师合作，优化设计以提高信号完整性，确保符合电气标准和高速设计最佳实践。
- 执行时域和频域分析，包括损耗、抖动和眼图分析。
- 使用EDA工具如Ansys SIWAVE、HFSS或类似工具进行信号完整性设计的仿真和验证。
- 与跨职能团队紧密合作，将信号完整性考虑纳入整体硬件设计流程。
- 根据测量的信号完整性数据开发行为模型，为未来的设计和仿真工作提供依据。
- 对高速信号接口进行布局前和布局后的仿真和测量。
要求
- 电子/电气工程学士或硕士学历，具有10年以上相关经验。
- 对电磁（EM）概念和传输线理论有深入理解。
- 在高速串行接口（包括以太网、PCIe和DDR5）的信号完整性分析方面有丰富经验。
- 熟练使用Ansys SIWAVE、HFSS或类似EDA工具。
- 具备实际操作经验
查看英文原文
Description
Senior Signal Integrity Engineer
About Us:
DriveNets is at the forefront of developing innovative solutions in high-speed electronics. Our cutting-edge technology serves the next generation of networking and communications, including Ethernet routers and high-performance platforms for the most demanding applications. We are committed to solving complex challenges and pushing the boundaries of what's possible in signal and power integrity.
The Role:
We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.
Responsibilities:
- Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
- Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
- Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
- Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
- Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
- Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
- Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
- Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
- Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.
Requirements
- Bachelor's or Master’s degree in Electrical/Electronics Engineering with 10+ years of relevant experience.
- Strong understanding of electromagnetic (EM) concepts and transmission line theory.
- Extensive experience in signal integrity analysis for high-speed serial interfaces, including Ethernet, PCIe, and DDR5.
- Proficiency in using EDA tools like Ansys SIWAVE, HFSS, or similar.
- Hands-on expertise in time-domain and frequency-domain analysis, jitter, loss, and eye-diagram analysis.
- Strong background in HSPICE simulations and model development.
- Experience with PCB layout techniques for high-speed designs.
- Excellent communication skills and the ability to work effectively in a collaborative team environment.
Advantages:
- Experience with advanced simulation tools and techniques.
- Experience with high-speed interfaces such as 112Gbps PAM4 Ethernet, PCIe Gen5, and DDR5.
- In-depth knowledge of high-speed PCB design and layout principles.
- Familiarity with power integrity and power noise simulations.
Originally posted on Himalayas