前端设计验证工程师
Front End Design Verification Engineer
Tenstorrent正在引领行业前沿的AI技术，重新定义性能预期、使用便捷性和成本效率。随着AI重新塑造计算范式，解决方案必须不断演进，以统一软件模型、编译器、平台、网络和半导体领域的创新。我们由多元化的技术人员组成，从零开始开发了一款高性能的RISC-V CPU，并对AI充满热情，渴望打造最佳的AI平台。我们重视协作、好奇心以及解决难题的承诺。我们正在扩大团队，寻找各层级的贡献者。
Tenstorrent正在寻找一名前端设计验证工程师，帮助验证我们下一代高性能RISC-V CPU核心的取指单元。你将负责确保处理器在正确的时间获取正确的指令——从指令取指和预测到解码和分发。你将与CPU架构师和RTL设计师紧密合作，制定验证策略，创建复杂的测试，调试复杂故障，并确保前端在各种工作负载和边界情况下行为正确。这是一个直接提升高性能乱序CPU性能和正确性的机会。
该职位为远程办公，位于北美或西班牙。
我们欢迎不同经验水平的候选人申请此职位。在面试过程中，将根据候选人的能力评估合适的级别，提供的offer将与该级别一致，可能与本职位描述中的级别不同。
你具备以下特质：
- 一位亲自动手的验证工程师，喜欢深入研究复杂的处理器行为并发现细微的错误。
- 熟悉CPU前端概念，如指令取指、分支预测、指令解码、队列和分发。
- 强大的问题解决能力，能够从规格说明、RTL、仿真和波形中识别根本原因。
- 具有协作精神和主动性，能够与架构师、RTL设计师和其他验证工程师密切合作。
- 对高性能CPU充满好奇，热衷于学习微架构决策如何影响实际处理器性能。
我们需要：
- 在CPU、SoC、ASIC或其他复杂数字设计的验证方面有6年以上经验。
- 精通SystemVerilog和UVM，包括约束随机测试、断言、功能覆盖率等。
查看英文原文
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for aFront End Design Verification Engineerto help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You’ll work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch. You’ll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This is an opportunity to make a direct impact on the performance and correctness of a high performance out-of-order CPU.
This role isremote, based out of North America or Spain.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs.
- Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch.
- A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes.
- Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers.
- Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance.
What We Need
- 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
- Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
- Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
- Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
- Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams.
What You Will Learn
- Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU.
- Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently.
- Develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes.
- Learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments.
- Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Originally posted on Himalayas