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CUDA工程师

CUDA Engineer

开发工程限定地区(需当地身份)日间重叠仅 1 小时,需熬夜配合
公司Fuse Energy
薪资未公开
工作地点United Kingdom
地域资格限定地区(需当地身份)
时区要求日间重叠仅 1 小时,需熬夜配合
用工类型Full Time
发布时间今天
数据来源Himalayas
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注意地域限制:该职位明确限定在 United Kingdom 招聘。如果你是位于中国大陆的求职者,通常需要当地工作身份才能投递,或需与雇主确认是否接受独立合同(Contractor)形式合作。
作息提示:日间重叠仅 1 小时,需熬夜配合。

Fuse Energy 是一家具有前瞻性的可再生能源初创公司,致力于快速提供一太瓦的可再生能源。我们结合基本原理思维与前沿技术,打造一个更加优越的能源系统。我们从包括 Multicoin、Balderton、Lakestar、Accel、Creandum、Lowercarbon、Ribbit、Box Group 在内的顶级投资机构以及 Nico Rosberg(Solana 联合创始人)等战略天使投资人处筹集了 2.1 亿美元资金。

随着数据中心成为电力需求最大且增长最快的来源之一,Fuse 正在扩展高性能计算基础设施,该领域位于能源与 AI 的交汇点——实时优化功率密集型 GPU 工作负载的调度、冷却,并根据电网状况进行平衡。

我们正在寻找一名 CUDA 工程师,负责编写和优化支撑我们推理工作负载的底层 GPU 代码。你将设计自定义 CUDA 内核,在内存带宽和计算瓶颈之间进行性能调优,并在每块 GPU 上实现最大吞吐量,工作层面涉及 SMs、warp 和内存层次结构。

职位机会
Fuse 正在与主要的 AI 计算客户进行积极洽谈,这些客户需要我们在运营市场中的数据中心容量,主要用于推理。目前的需求远超我们当前的建设能力,这意味着供电速度、可靠性和部署成本比具体硬件选择更为重要。这使得 CUDA/GPU 性能工程成为 Fuse 服务市场上最大计算买家的核心。

职责

  • 为核心 transformer 推理操作编写和优化自定义 CUDA 内核。
  • 对内核进行分析,识别并消除在占用率、内存吞吐量和 warp 发散方面的瓶颈。
  • 应用内核融合以减少推理流水线中的内存往返次数和启动开销。
  • 优化内存访问模式并管理内存层次结构,以实现最大带宽利用率。
  • 实现感知量化内核和混合精度算术,以降低延迟和内存占用。
  • 构建并调优缓存机制,以实现高效的自回归解码。
  • 针对目标 GPU 架构调整内核启动配置。
  • 将内核与现有基准进行对比测试,并推动可衡量的吞吐量和延迟改进。
  • 为 CUDA 代码编写测试,以捕捉性能和正确性退化。
  • 维护内部 CUDA 库并做出贡献
查看英文原文

Fuse Energy is a forward-thinking renewable energy startup on a mission to deliver a terawatt of renewable energy - fast. We're combining first-principles thinking with cutting-edge technology to build a radically better energy system. We raised $210M from top-tier investors including Multicoin, Balderton, Lakestar, Accel, Creandum, Lowercarbon, Ribbit, Box Group and strategic angels like Nico Rosberg, the Co-Founder of Solana and GPs behind Meta, Revolut, Spotify, Uber and more.
As data centers become one of the largest and fastest-growing sources of electricity demand, Fuse is expanding into high-performance compute infrastructure that sits at the intersection of energy and AI - optimising how power-dense GPU workloads are scheduled, cooled, and balanced against grid conditions in real time.
We're looking for a CUDA Engineer to write and optimise the low-level GPU code that powers our inference workloads. You'll design custom CUDA kernels, tune performance across memory bandwidth and compute bottlenecks, and squeeze maximum throughput out of every GPU in our fleet, working at the level of SMs, warps, and memory hierarchies.
The Opportunity
Fuse is in active discussions with major AI compute customers who need data center capacity across the markets we operate in, primarily for inference. Demand significantly outpaces what we can currently build, meaning speed to power, reliability, and deployment cost matter more than specific hardware choice. This puts CUDA/GPU performance engineering at the center of how Fuse serves some of the largest compute buyers in the market.
Responsibilities

  • Write and optimise custom CUDA kernels for core transformer inference operations.
  • Profile kernels to identify and eliminate bottlenecks in occupancy, memory throughput, and warp divergence.
  • Apply kernel fusion to reduce memory round-trips and launch overhead across inference pipelines.
  • Optimise memory access patterns and manage the memory hierarchy for maximum bandwidth utilisation.
  • Implement quantisation-aware kernels and mixed-precision arithmetic to reduce latency and memory footprint.
  • Build and tune caching mechanisms for efficient autoregressive decoding.
  • Tune kernel launch configurations for target GPU architectures.
  • Benchmark kernels against existing baselines and drive measurable throughput and latency improvements.
  • Write tests for CUDA code to catch performance and correctness regressions.
  • Maintain internal CUDA libraries and contribute to team coding standards and documentation.

Requirements
· 4+ years writing production CUDA code, with a track record of shipping performance-critical kernels.

  • Deep understanding of GPU microarchitecture, warps, occupancy, register pressure, and memory hierarchy.
  • Strong CUDA C++ skills, including streams and asynchronous execution.
  • Hands-on experience profiling to diagnose compute-bound vs. memory-bound bottlenecks.
  • Experience with kernel fusion, memory coalescing, and avoiding warp divergence.
  • Experience writing quantised and mixed-precision kernels.
  • Solid grasp of parallel algorithm design and numerical precision tradeoffs.

Nice to Have

  • Experience with transformer/attention-style kernels or autoregressive decoding.
  • Experience building high-performance GPU libraries from scratch.
  • Background in HPC or other latency-critical performance engineering.
  • Exposure to multi-GPU or multi-node kernel-level optimisation.
  • Comfortable reading PTX/SASS to validate kernel efficiency.

Benefits

  • Competitive salary and an equity sign-on bonus.
  • Biannual bonus scheme.
  • Fully expensed tech to match your needs.
  • Breakfast and dinner allowance for office based employees.

Originally posted on Himalayas

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