RTL设计工程师 – 互连与网络数据路径
RTL Design Engineer – Interconnect & Network Datapath
关于团队
OpenAI 的硬件部门为先进 AI 工作负载的独特需求开发原生 AI 芯片和系统级解决方案。在 Jalapeño 等工作的基础上，该团队正在开发下一代原生 AI 芯片和高度集成的系统，以支持前沿模型的下一次迭代。通过芯片、系统、工具和方法的协同设计，该团队帮助为 OpenAI 的超算平台交付更快、更高效且可投入生产的硬件。
关于职位
我们正在寻找一位经验丰富的、动手能力强的 RTL 工程师，具备深厚的包网络和互连专业知识，负责我们定制 AI 加速器平台的关键片上和片外通信组件。
你将主导连接高带宽计算、内存和 I/O 子系统的可扩展片上结构的微架构和 RTL 实现，以及专为大规模定制计算设计的片外接口和协议。理想的候选人最近曾负责网络或包交换数据路径的生产级 RTL，例如以太网交换机、网卡（NIC）、智能网卡（SmartNIC）、网络加速器、RDMA/RoCE 系统、NoC 或自定义的扩展上/扩展外结构。
这是一个高级工程职位，拥有广泛的工程技术职责和大量的直接 RTL 工作。你将从需求和性能分析开始，推动设计经过微架构、SystemVerilog 实现、验证闭合、物理设计收敛、芯片启动和生产就绪。你还将计划和监督初级工程师的工作，并与外部合作伙伴建立高效的工程关系。
在此职位中，你将：
- 负责主要基于包的互连和网络组件的微架构、RTL 设计和交付，包括 NoC 结构、交换机、路由器、桥接器、协议适配器、仲裁器、队列、调度器、缓冲器和流量管理逻辑。
- 设计路由、仲裁、排序、流量控制、拥塞管理、服务质量、包调度、缓冲和性能监控的机制。
- 开发片上和片外接口、协议桥接器以及用于扩展上和扩展外系统的自定义网络协议或协议扩展。
- 执行大量的直接微架构、SystemVerilog 编码、仿真和调试工作。
- 与架构和性能团队合作，分析流量模式，识别瓶颈，并优化性能。
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ABOUT THE TEAM
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
ABOUT THE ROLE
We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform.
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics.
This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners.
IN THIS ROLE, YOU WILL:
- Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic.
- Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring.
- Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems.
- Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.
- Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads.
- Work with verification teams to develop coverage plans, assertions, stress scenarios, and debug strategies for highly concurrent packet and fabric behavior.
- Partner with physical design teams on floorplan-aware design, pipeline strategy, timing closure, power, area, and physical congestion.
- Collaborate with firmware, software, validation, and post-silicon teams through bring-up and production readiness.
- Drive third-party engagements involving networking, interface protocols, and silicon IP while maintaining design quality and execution accountability.
- Provide technical leadership through architecture and design reviews, documentation, mentoring, and reusable RTL methodologies.
YOU MIGHT THRIVE IN THIS ROLE IF YOU HAVE:
- Extensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.
- Demonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic management, or custom scale-up/scale-out transports.
- Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
- A strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.
- Experience designing queues, arbiters, schedulers, buffers, routing logic, virtual channels, credit-based flow control, congestion management, quality of service, ordering, or deadlock-avoidance mechanisms.
- Experience with relevant on-chip, chip-to-chip, or host interfaces such as AXI, CHI, CXL, PCIe, or Ethernet, alongside deeper networking or packet-datapath expertise.
- Experience designing custom networking protocols, protocol extensions, or hardware datapaths for large-scale RDMA/RoCE, HPC, or AI systems.
- Strong familiarity with RTL development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.
- Experience collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
- Strong judgment when balancing performance, power, area, schedule, verification risk, and physical implementation constraints.
- The ability to provide technical direction, mentor engineers, and drive alignment while remaining actively involved in RTL design and debugging.
- A passion for reducing complexity and improving engineering leverage through automation and pragmatic design.
PREFERRED QUALIFICATIONS
- Experience designing packet-switched interconnect or networking datapaths for AI accelerators, GPUs, CPUs, HPC systems, NICs/SmartNICs, switch ASICs, or large-scale datacenter silicon.
- Experience addressing virtualization, isolation, RAS, telemetry, security, or memory-consistency requirements within complex networking or interconnect subsystems.
- Experience with network or NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon traffic and performance analysis.
- Experience leading architecture or RTL delivery for first-generation networking or interconnect IP in rapidly evolving silicon programs.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
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