ASIC设计工程师
ASIC Design Engineer
**关于 Positron AI**
Positron AI 专注于开发定制硬件系统以加速 AI 推理。这些推理系统相比传统的基于 GPU 的系统，在性能和效率方面都有显著提升，带来了每美元性能和每瓦性能的优势。Positron 的目标是打造世界上最好的 AI 推理系统。
**职位概述**
作为高级 ASIC 设计工程师，您将在定义、实现和交付 Positron.ai 推理 ASIC/SoC 的关键 IP 模块和子系统中发挥领导作用。您将从高层次概念到 RTL 签收，负责微架构的设计，与架构、验证和物理设计团队协作，实现具有挑战性的 PPA 和时间表目标。除了亲自进行 SystemVerilog 设计外，您还将指导初级工程师，影响方法论，并推动影响硅片性能和效率的关键架构权衡。
**主要职责**
**微架构与 RTL 领导：**
- 定义并记录复杂 IP 模块/子系统的微架构。
- 提供高质量、参数化的 SystemVerilog RTL，具有明确的接口、电源/时钟意图和嵌入式断言。
**技术责任与签收：**
- 主导 lint、CDC/RDC、DFT 集成和综合启动；与 PD 合作进行 floorplan 和时序闭合。
- 负责所分配模块的 PPA 指标，并推动微架构优化以达到目标。
**高级接口与内存集成：**
- 设计并集成高性能互连（AXI/CHI/ACE）、DMA 引擎、一致性逻辑和高速内存接口（HBM/DDR）。
- 与 IP 供应商和内部利益相关者合作，确保无缝集成。
**方法论与最佳实践：**
- 开发并执行编码规范、可重用 IP 打包和签收检查清单。
- 贡献自动化流程（Python/Tcl/Make/CI）以提高团队效率。
**跨职能协作：**
- 与验证团队紧密合作，定义测试计划和参考模型。
- 与架构和性能团队协作，将模型与 RTL 对应。
- 在需要时支持启动、后硅调试和客户对接。
**指导与技术领导：**
- 指导初级工程师在设计技巧、方法论和问题解决方面的成长。
- 主持设计评审，推动对权衡的共识，并倡导最佳解决方案。
**所需资格**
- 电子工程或相关专业本科/硕士学历
查看英文原文
**About Positron AI**
Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
**Role Overview**
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.
**Key Responsibilities**
**Microarchitecture & RTL Leadership:**
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
**Technical Ownership & Signoff:**
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
**Advanced Interface & Memory Integration:**
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Engage with IP vendors and internal stakeholders to ensure seamless integration.
**Methodology & Best Practices:**
- Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
- Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
**Cross-Functional Collaboration:**
- Partner closely with Verification to define test plans and reference models.
- Work with Architecture and Performance teams to correlate models against RTL.
- Support bring-up, post-silicon debug, and customer engagements as required.
**Mentorship & Technical Leadership:**
- Guide junior engineers in design techniques, methodology, and problem-solving.
- Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.
**Required Qualifications**
- BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
**Preferred Qualifications**
- Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
- Formal verification/SVA expertise for property checking and design assertions.
- Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
- Collaboration experience with cocotb/UVM for checkers and reference model co-development.
- Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.
**Leveling & Scope**
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
**Why Join Us?**
- Shape the next generation of AI inference hardware with a high-caliber, collaborative team.
- Take technical ownership of critical silicon components that directly impact product success.
- Competitive salary + equity, comprehensive benefits, and flexible work environment.
- Opportunities to innovate, lead, and grow your influence in a rapidly evolving space.
**Compensation and Benefits**
The base salary range for this role is $225,000 – $350,000.
Please note that the figures provided represent the **base salary range only** and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, **we reserve the flexibility to exceed this range** for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
**Equal Opportunity Employer.** If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.