高级SerDes系统/DSP设计工程师
Senior SerDes System/DSP Design Engineer
作为高速连接领域的全球领导者，Ciena 坚持以人为本的理念。我们的团队拥有一个以灵活工作环境为核心的文化，注重个人成长、福祉和归属感。我们是一家技术公司，以人文精神引领——在推动业务目标的同时，也关注有意义的社会、社区和影响力。
我们正在构建下一代 448G 电气 SerDes，并开创光学 IMDD 系统，为未来的网络提供动力。我们的工程团队位于高性能 DSP 设计、系统建模和光学创新的交汇点。
您将如何贡献：
我们正在寻找一位高技能的高级 SerDes 系统/DSP 设计工程师加入我们的高级工程团队。在此职位中，您将负责跨电气和光学领域的高速串行收发器的架构、设计和验证。您将利用系统工程、控制理论、DSP 算法和建模方面的专业知识，开发先进的串行电气/光-IMDD 收发器解决方案。
此职位提供了在电气 SerDes 技术和先进光通信交叉领域参与行业领先设计的机会，推动实现下一代高容量网络的创新。
- 领导高速数据通信系统中电气 SerDes DSP 架构的设计与开发。
- 执行 SerDes 收发器解决方案的系统级评估、建模和性能分析，包括失真和缓解技术。
- 开发自适应均衡、最大似然序列检测（MLSD）和定时恢复算法的算法和架构。
- 将控制理论和先进的 DSP 设计整合到可行的硬件实现中。
- 与跨职能团队（模拟设计、ASIC 设计、光电硬件、固件）合作，优化端到端系统的 SerDes 性能。
- 进行设计权衡，以满足严格的性能、功耗和面积目标。
- 分析信道模型、模拟电路失真（DAC、ADC、AFE、…）和系统约束，确定系统级余量和 FEC（前向纠错）性能，并优化系统余量。
- 为 SerDes 收发器的不同子模块（如 DAC、ADC、AFE、PLL）提供系统级规格。
- 评估和建模 IMDD 光学链路，并制定策略以增强系统鲁棒性。
查看英文原文
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
We’re building the next generation of 448G electrical SerDes and pioneering optical IMDD systems to power tomorrow’s networks. Our engineering team lives at the intersection of high-performance DSP design, system modeling, and optical innovation.
How You Will Contribue:
We are seeking a highly skilled Senior SerDes System/DSP Design Engineer to join our advanced engineering team . In this role, you will lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains. You will leverage your expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions.
This position offers the opportunity to work on industry-leading designs at the intersection of electrical SerDes technology and advanced optical communications, driving innovations that enable next-generation high-capacity networks.
- Lead the design and development of electrical SerDes DSP architectures for high-speed data communication systems.
- Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques.
- Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms.
- Integrate control theory and advanced DSP designs into feasible hardware implementations.
- Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems.
- Conduct design trade-offs to meet stringent performance, power, and area targets.
- Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.
- Provide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL.
- Evaluate and model IMDD optical links and formulate strategies to enhance system robustness.
- Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps.
The Must Haves
- Advanced expertise in electrical SerDes DSP design and implementation.
- Proven experience in SerDes system-level evaluation, modeling, and simulation.
- Strong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems.
- Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems.
- Deep understanding of adaptive equalization techniques for high-speed links.
- Proficiency with maximum likelihood sequence detection (MLSD) approaches.
- Expertise in timing recovery schemes in high-speed serial links.
- Practical knowledge of FEC performance modeling and system-level performance optimization.
- Experience with MATLAB, Python, or C/C++ for algorithm design and simulation.
- Strong problem-solving skills and ability to work across hardware/software boundaries.
- Ph.D. in Electrical Engineering with background in digital communications and signal processing.
- 8+ years of experience in high-speed serial link or communication system design.
Nice to Haves:
- Knowledge of industry standards such as PCIe, IEEE, Ethernet, or OIF standards for optical communication.
- Hands-on experience with lab bring-up, characterization, and debugging of SerDes links.
Pay Range:
The annual salary range is $126,100 - $201,500 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Originally posted on Himalayas