中端ASIC工程师
Mid-End ASIC Engineer
**关于 Positron AI**
Positron AI 专注于开发定制的硬件系统以加速 AI 推理。这些推理系统相比传统的 GPU 系统在性能和效率上都有显著提升，带来了每美元性能和每瓦性能的优势。Positron 的目标是打造全球最佳的 AI 推理系统。
### **职位概述**
我们正在寻找一位卓越的高级中端 ASIC 工程师，负责我们 AI 加速器路线图中的综合、时序收敛、实现准备和逻辑设计质量。这是一项高度技术性、动手能力强的工程岗位，负责将高质量的 RTL 转换为可实现的网表，同时推动时序闭合策略、约束开发、物理感知优化，并与 RTL 设计师和后端实现合作伙伴紧密协作。你将成为架构、RTL、验证和物理实现之间的技术桥梁。
### **主要职责**
**综合方法与责任**
- 在当前和未来的 ASIC 代际中定义并负责综合方法，包括可扩展的 RTL 综合流程、约束开发、时序预算、QoR 优化、增量综合和分层实现。
- 建立综合交付物的签收标准和方法。
**实际操作的综合与约束开发**
- 使用行业领先的 EDA 工具（如 Cadence Genus 和 Synopsys Design Compiler 或等效工具）进行实际操作的综合。
- 开发和维护 SDC 约束、时钟定义、虚假路径、多周期路径、生成时钟和 MMMC 环境。
- 推动综合 QoR 的持续改进。
**时序闭合领导力**
- 负责逻辑时序闭合，并推动频率、面积、功耗、拥塞和布线能力的优化。
- 对时序瓶颈进行根本原因分析，并在所有芯片分区中制定时序预算。
- 与架构和 RTL 团队紧密合作，在物理实现之前消除时序风险。
**物理感知优化**
- 与后端实现工程师紧密合作，推动物理感知综合、重定时、寄存器平衡、流水线优化、逻辑重构和分层时序预算。
- 确保 RTL 从一开始就具备实现友好性。
**跨职能执行**
- 与架构、RTL、验证和物理实现团队紧密合作
查看英文原文
**About Positron AI**
Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
### **Role Overview**
We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.
### **Key Responsibilities**
**Synthesis Methodology & Ownership**
- Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
- Establish signoff criteria and methodology for synthesis deliverables.
**Hands-On Synthesis & Constraint Development**
- Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
- Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
- Drive continuous improvement of synthesis QoR.
**Timing Closure Leadership**
- Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability.
- Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions.
- Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation.
**Physical-Aware Optimization**
- Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.
- Ensure RTL is implementation-friendly from the outset.
**Cross-Functional Execution**
- Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
**Vendor Technical Leadership**
- Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.
**AI-Enabled Engineering**
- Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
### **Required Qualifications**
- 12+ years of ASIC implementation experience, including multiple successful tapeouts.
- Expert-level proficiency in synthesis methodology and flow development.
- Deep expertise in timing closure across complex, multi-million-gate designs.
- Expert-level command of Cadence Genus and/or Synopsys Design Compiler.
- Strong SDC expertise, including constraint development and MMMC environments.
- A solid grasp of RTL design principles and implementation-friendly coding practices.
- Hands-on experience with advanced process nodes at 5nm and below.
- Strong Tcl and Python scripting ability for automation and flow development.
- Excellent debugging and root-cause analysis skills.
### **Preferred Qualifications**
- Experience with AI accelerators, CPUs, or GPUs.
- Familiarity with LPDDR, PCIe, or SerDes interfaces.
- Exposure to chiplet-based architectures and multi-clock SoC designs.
#### **Leveling & Scope**
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
### **What Success Looks Like**
Within one year, this person will have established a production-grade synthesis methodology, delivered predictable timing closure, reduced implementation iterations, produced high-quality implementation-ready RTL, and built a scalable methodology to support future ASIC generations.
### **Why Join Us?**
- Play a foundational role in shaping the synthesis and timing closure methodology for next-generation AI inference accelerators.
- Work at the cutting edge of AI hardware, directly influencing chips built to power frontier AI workloads.
### **Compensation & Benefits**
The base salary range for this role is $190,000 – $280,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
### **Benefits & Perks**
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
**Health and wellness**
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
**Time off and flexibility**
- Unlimited paid time off — we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
**Compensation and future**
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
### **Visa Support**
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
**Equal Opportunity Employer.** If you're excited about the role but don't meet every bullet, we'd still love to hear from you.