远程工作雷达

仿真测试工程师

Emulation Test Engineer

开发工程限定地区(需当地身份)与中国几乎无重叠,需长期倒时差
公司Positron AI
薪资未公开
工作地点United States
地域资格限定地区(需当地身份)
时区要求与中国几乎无重叠,需长期倒时差
用工类型permanent
发布时间26 天前
数据来源4dayweek.io
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注意地域限制:该职位明确限定在 United States 招聘。如果你是位于中国大陆的求职者,通常需要当地工作身份才能投递,或需与雇主确认是否接受独立合同(Contractor)形式合作。
作息提示:与中国几乎无重叠,需长期倒时差。

**关于 Positron AI**

Positron AI 专注于开发定制硬件系统以加速 AI 推理。这些推理系统相比传统 GPU 系统在性能和效率方面有显著提升,带来了每美元和每瓦特性能的优势。Positron 的目标是打造世界上最好的 AI 推理系统。

**关于该职位**

作为仿真测试工程师,你将为 Positron 下一代 AI 推理 ASIC 的硅前验证提供技术指导。你将负责 Cadence Palladium 平台上的端到端仿真策略,设计复杂的模型构建,管理多机架分区,并推动软件开发的“左移”。你将与 RTL、DV 和软件团队合作,构建高性能的虚拟环境,验证架构功能,并在流片前数月加速固件/操作系统启动。该职位对我们的芯片成功至关重要:你将制定仿真方法,解决大规模的软硬件瓶颈,并确保我们的设计具备流片条件。

**你会做什么**

- **大规模模型架构:** 领导在多机架 Palladium 环境中对我们的设计进行分区和编译,优化性能和调试可见性。
- **软件使能(左移):** 创建并维护混合仿真和共仿真环境(使用 **SCE-MI** 或 **DPI**),使我们的软件团队能够在硅前硬件上启动操作系统镜像并运行 AI 工作负载。
- **全栈验证:** 设计并执行全面的仿真测试计划,验证高速接口( **PCIe Gen 6/7, 112G+VSR, Ethernet**)和复杂的 AI 内存层次结构。
- **性能与功耗分析:** 利用 Palladium 的 **动态功耗分析 (DPA)** 和吞吐量监控器,识别仿真无法捕捉的“真实峰值”和性能瓶颈。
- **供应商管理:** 作为与 Cadence R&D 的主要技术联系人,解决工具问题并利用最新的 **Palladium Z3** 功能。

**如果你具备以下条件,你将在这里取得成功**

- **深厚的 Palladium 专业知识:** 在 **Cadence Palladium (Z1/Z2/Z3)** 上有丰富的实战经验,包括高级时钟设置、ICE(在线仿真)和虚拟接口(VIF)流程
- **复杂 SoC 背景:** 有模拟数十亿门设计的经验,包括分区、运行时可预测性和编译效率

查看英文原文

**About Positron AI**

Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.

**About the role**

As Emulation Test Engineer, you'll provide technical direction for pre-silicon validation of Positron's next-generation AI inference ASIC. You'll own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and driving the "left-shift" of our software development. You'll collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you'll set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.

**What you'll do**

- **Massive-Scale Model Architecture:** Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
- **Software Enablement (Left-Shift):** Create and maintain the hybrid emulation and co-simulation environments (using **SCE-MI** or **DPI**) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
- **Full-Stack Validation:** Design and execute comprehensive emulation test plans to verify high-speed interfaces ( **PCIe Gen 6/7, 112G+VSR, Ethernet**) and complex AI memory hierarchies.
- **Performance & Power Analysis:** Utilize Palladium’s **Dynamic Power Analysis (DPA)** and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture.
- **Vendor Management:** Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest **Palladium Z3** capabilities.

**You'll Be Successful Here if You Have**

- **Deep Palladium Expertise:** Extensive hands-on experience with **Cadence Palladium (Z1/Z2/Z3)**, including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
- **Complex SoC Background:** A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
- **Automation Mastery:** Expert-level **Python**, **Tcl**, and **Bash** skills to build and maintain the infrastructure for automated model releases and nightly regressions
- **Hardware-Software Debug Skills:** Proficiency in debugging low-level firmware and kernel-level issues using **Verdi**, **SimVision**, and hardware-software co-debug tools

**Minimum Requirements**

- **Education:** BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
- **Experience:** 8+ years in **ASIC Emulation** or Verification, with significant experience on large-scale Palladium installations
- **Technical Skills:** Mastery of **SystemVerilog**, **Verilog**, and **C/C++** for transactor development and reference modeling.
- **Protocol Knowledge:** Deep understanding of data center protocols including **PCIe**, **DDR** and **AMBA AXI/NoC**

**Leveling & Scope**

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

**Compensation & Benefits**

The base salary range for this role is $180,000 – $300,000.

Please note that the figures provided represent the **base salary range only** and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, **we reserve the flexibility to exceed this range** for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.

### **Benefits & Perks**

We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.

**Health and wellness**

- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available

**Time off and flexibility**

- Unlimited paid time off — we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup

**Compensation and future**

- Competitive salary and equity
- 401(k) with company matching, eligible from day one

### **Visa Support**

This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.

**Equal Opportunity Employer.** If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.

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