3D Chiplet Engineer
我们正在解决AI计算中遇到的物理瓶颈，内存瓶颈正在拖慢整个行业。2024年10月成立，获得5700万欧元资金支持，Vertical Compute通过专有的垂直集成内存（VIM™）芯片模块解决了这一问题，使AI硬件更快、更环保，并且可扩展性更强。我们是一个跨学科团队，将突破性的半导体物理转化为商业现实。
现在正是时候：经过18个月的密集研发，Vertical Compute已到达关键转折点。我们的核心技术已得到验证，我们已成功实现核心技术里程碑。凭借经过验证的技术数据包和持续的系统研究，我们现在从纯研发转向与全球企业客户的积极合作。在我们为2027年开始的下一阶段规模和增长做准备时，今天加入我们意味着直接负责将推动下一代AI计算的硬件基础。
职位简介：
我们正在寻找一位3D集成/芯片模块专家，为我们的垂直集成内存（VIM）技术定义并实施2.5D/3D先进封装解决方案。你将跨团队协作，定义最优的互连策略和芯片堆叠方法，以实现高带宽、低功耗运行。该职位位于SoC架构（特别是物理设计）、封装设计和3D制造工艺的交汇点。
主要职责：
- 集成架构与工艺定义：
- 制定VIM芯片模块与计算芯片模块的2.5D/3D堆叠架构。
- 与设计和技术团队合作，开发确保高带宽和低延迟的互连解决方案。
- 明确芯片模块物理设计对芯片模块的影响（包括硅通孔、微凸点、混合键合、重分布层和芯片模块接口等）。
- 与代工厂、封装合作伙伴和内部物理设计团队定义制造流程和设计规则。
- 性能分析与仿真：
- 进行早期多物理场仿真（热、电、机械），分析并优化集成系统的性能和可靠性。
- 推动外部合作伙伴完成最终封装设计。
- 协作与沟通：
- 与设计、工艺工程、计量和系统架构团队紧密合作。
- 参与会议、标准化组织和行业活动，推动或主导关于...的讨论。
查看英文原文
About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a 3D Integration / Chiplet Expert to define and implement 2.5D/3D advanced packaging solutions for our Vertical Integrated Memory (VIM) technology. You will collaborate across teams to define optimal interconnect strategies and die stacking approaches to enable high-bandwidth, low-power operation. This job sits at the intersection of SoC architecture (specifically the physical design) , package design, and 3D manufacturing processes.
Key Responsibilities:
- Integration Architecture & Process Definition:
- Develop and define architectures for 2.5D/3D stacking of VIM chiplets with compute chiplets.
- Collaborate with design and technology teams to develop interconnect solutions that ensure high bandwidth and low latency.
- Define clearly the impact of the chiplet physical design chiplets (through-silicon vias, micro-bumps, hybrid bonds, redistribution layers, and chiplet interfaces, …)
- define fabrication flows and design rules with foundries, packaging partners, and internal physical design teams
- Performance Analysis & Simulation: Conduct early multi-physics simulations (thermal, electrical, mechanical) to analyze and optimize the performance and reliability of integrated systems.
- drive external partners for final package design
- Collaboration & Communication:Partner closely with design, process engineering, metrology, and system architecture teams.
- Participate in conferences, standardization bodies and industry events to promote or lead discussions about the future of chiplet integration.
- Technical Leadership:Provide
- technical leadership and project management guidance to multidisciplinary teams.
About the team:
This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
Requirements
About who you are:
- You’ve spent 5–10 years exploring the frontiers of 2.5D/3D packaging and heterogeneous integration, turning complex ideas into manufacturable systems.
- You have a deep understanding on the SoC physical design, TSVs, Redistribution Layers, hybrid bonding and how they are used at system level to implement chip IOs (Functional and power IOs)
- You are mastering Integrity 3D-IC Platform to define the chiplets interface, to define 3D stacking system, to generate the 3Dblox views, and to run all the 3D system level analysis (Power Delivery Network, Thermal, STA, LVS, SI/PI, …)
- You thrive where architecture meets technology — translating ambitious concepts into elegant, high-performance designs.
- Multi-physics isn’t just theory to you; you use thermal, electrical, and mechanical simulations to see the whole system clearly.
- You’re naturally collaborative — just as comfortable in technical deep dives as you are building bridges between design, process, and system teams.
- You’re the kind of engineer who balances vision with execution: leading projects, mentoring peers, and pushing boundaries with a calm hand.
- Above all, you’re curious — drawn to the challenge of building something new and meaningful at the intersection of memory, compute, and packaging innovation.
- Fluency in English with strong written and verbal communication abilities.
Why Join Us:
- You will get the opportunity to work at the forefront of memory technology innovation.
- Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
- You can be part of a talented and dedicated team in a fast-paced startup environment.
- In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
- You can count on a motivating total rewards package.
- Flexible ways of working.
Join us in shaping the future of compute & memory technology — and celebrating success!
Originally posted on Himalayas