RTL验证工程师
RTL Verification Engineer
关于公司：AI计算正面临物理瓶颈，内存瓶颈正在拖慢整个行业。2024年10月成立，获得5700万欧元资金支持，Vertical Compute通过专有的垂直集成内存（VIM™）芯片解决方案突破这一困境，使AI硬件更快、更环保、可扩展性更强。我们是一个跨学科团队，将突破性的半导体物理技术转化为商业现实。
为何现在加入：经过18个月的密集研发，Vertical Compute已到达关键转折点。我们的核心技术已验证，核心关键技术里程碑已达成。凭借经过验证的技术数据包和持续的系统研究，我们现在从纯研发转向与全球企业客户的积极合作。在2027年开始下一阶段的规模和增长之前，今天加入我们意味着直接负责构建将推动下一代AI计算的硬件基础。
职位介绍：
我们正在寻找一名RTL验证工程师，负责并执行Vertical Compute 3D集成芯片的验证工作。在此职位中，您将专注于芯片的顶层验证。将高性能AI加速器直接与我们的专有垂直集成内存（VIM™）结合，这些芯片展示了我们技术的全部能力，以满足AI市场的需求。
主要职责：
- 领导下一代AI计算芯片的顶层功能验证，确保完整的协议合规性和强大的多芯片集成。
- 设计、部署和维护针对内存和计算子系统的高级UVM/SystemVerilog测试平台、断言和约束随机测试计划。
- 推动覆盖率驱动的验证，针对复杂软硬件边界场景进行目标调试和根本原因分析。
- 与前端RTL设计、系统架构和软件/编译器团队紧密合作，实现完整的流片准备和硅后验证。
- 对系统级性能进行基准测试和分析，展示Vertical Compute VIM™技术的吞吐量、带宽和能效。
关于团队：
该职位是Vertical Compute产品与系统组织中硬件设计团队的一部分，直接向硬件团队经理汇报。您将与前端设计和软件团队密切合作，跨职能工程组进行协作。
查看英文原文
About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for an RTL Verification Engineer to lead and execute the verification of our Vertical Compute's 3D-integrated chiplets. In this role, you will specifically focus on the top-level verification of the chiplets. Coupling high-performance AI accelerators directly with our proprietary Vertical Integrated Memory (VIM™), these chiplets showcase the full capabilities of our technology to address the AI market.
Key Responsibilities:
- Lead top-level functional verification for our next-generation AI compute chiplet, ensuring complete protocol compliance and robust multi-die integration.
- Architect, deploy, and maintain advanced UVM/SystemVerilog testbenches, assertions, and constrained-random test plans for memory and compute subsystems.
- Drive coverage-driven verification, target debug, and root-cause analysis across complex hardware-software boundary scenarios.
- Collaborate closely with Front-End RTL Design, System Architecture, and Software/Compiler teams to achieve full tape-out readiness and post-silicon validation.
- Benchmark and analyze system-level performance to demonstrate the throughput, bandwidth, and energy efficiency of Vertical Compute's VIM™ technology.
About the team:
This role is part of the Hardware Design team within Vertical Compute's Product & System organization, reporting directly to the HW Team Manager. You will work in close collaboration with the Front-End Design and Software teams, partnering across cross-functional engineering groups to ensure the seamless functionality, performance, and successful delivery of our vertical compute products.
Requirements
About who you are:
- Proven track record in ASIC/SoC functional verification, including top-level verification of complex multi-IP designs or AI compute accelerators.
- Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
- Strong expertise in SystemVerilog, UVM (Universal Verification Methodology), assertion-based verification, and coverage-driven verification for complex hardware architectures.
- Strong collaborative mindset and problem-solving skills to work effectively with cross-functional FE Design, System, and SW teams.
- Fluency in English with excellent written and verbal communication skills.
Highlights
Leading and mentoring engineering teams, managing projects from concept to silicon qualification, and collaborating with key industry partners to deliver innovative memory solutions.
Originally posted on Himalayas