混合信号IC布局工程师
Mixed Signal IC Layout Engineer
Tenstorrent正在引领前沿AI技术的发展，重新定义性能预期、使用便捷性和成本效率。随着AI重塑计算范式，解决方案必须不断进化，以统一软件模型、编译器、平台、网络和半导体领域的创新。我们由多元化的技术团队组成，从零开始开发了高性能的RISC-V CPU，并对AI充满热情，渴望打造最优秀的AI平台。我们重视协作、好奇心和解决难题的承诺。我们正在扩大团队，寻找各层级的贡献者。
Tenstorrent正在招聘一名混合信号IC布局设计工程师，该职位涉及模拟和混合信号集成电路的全定制物理布局，将原理图转化为符合先进FinFET工艺中性能、功耗、面积和可靠性目标的可制造布局。该职位专注于高质量、高速模拟/混合信号模块及其在更大SoC中的集成。
该职位为远程办公，工作地点在美国任何地方。
我们欢迎不同经验水平的候选人申请该职位。在面试过程中，将评估候选人的适当级别，提供的offer将与该级别一致，可能与本职位描述中的级别不同。
你是什么样的人
- 具有丰富的模拟/混合信号IC布局经验，具备高速模块（PLLs、VCOs、ADCs、DACs、LDOs、比较器、时钟生成器、高速I/O）的完整定制布局背景。
- 熟练使用Synopsys Custom Compiler或Cadence Virtuoso进行定制布局，以及Synopsys ICV或Siemens Calibre进行物理验证（DRC、LVS、ERC、DFM、天线）。
- 深入了解CMOS/FinFET节点（理想情况下为TSMC或三星12nm–2nm），具有已交付硅片的经验，并对混合信号布局中的EM/IR、ESD和闩锁有深刻理解。
- 注重细节且有条理，能够独立负责复杂模块并有效与电路设计师合作；通常拥有BSEE学位（或同等经验），并在模拟/混合信号布局领域有10年以上经验。
我们需要什么
- 从原理图到可制造布局，执行关键模块（PLLs、VCOs、ADCs、DACs、LDOs、带隙基准、比较器、时钟生成器、高速I/O）的全定制模拟/混合信号布局。
- 开发优化的模块和顶层布局规划、放置和布线，平衡面积、寄生效应、匹配度、拥塞情况及与我们D2D PHY的集成。
查看英文原文
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.
This role is remote, based out of any in the United States.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who you are
- An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
- Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
- Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
- Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.
What we need
- Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
- Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
- Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
- Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.
What you will learn
- Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.
- How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.
- Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.
- How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Originally posted on Himalayas