负责人ASIC DFT工程师
Lead ASIC DFT Engineer
我们正在寻找一位经验丰富的首席ASIC DFT工程师，负责为复杂的ASIC和SoC设计构建、实现、验证和调试先进的DFT解决方案。该职位需要在DFT架构、扫描插入、ATPG、MBIST/LBIST、JTAG、边界扫描和后硅验证等方面具备深入的技术能力，同时能够领导跨职能的调试工作并推动解决关键硅片问题。
理想的候选人应具备扎实的DFT基础技能，包括故障模型、测试覆盖率、诊断和调试能力，以及评估和采用新兴DFT方法和架构方案的能力，以提升产品的鲁棒性、质量和良率
要求
必备技能与资格
- 在ASIC DFT方面有扎实的动手经验和全流程主导能力。
- 熟悉DFT基础、故障模型、测试技术及测试覆盖率概念。
- 在扫描架构、ATPG、MBIST、LBIST、JTAG、边界扫描和硅片调试方面有深厚的专业知识。
- 有使用Synopsys、Cadence和Siemens/Mentor EDA工具的实际经验。
- 有扫描插入、ATPG设置、仿真、调试和DRC分析的实际经验。
- 有MBIST实现和验证经验；有SMS经验者优先。
- 有扫描架构和扫描链连接经验；有Tessent/SSN经验者优先。
- 熟悉PLL、RTL设计、综合流程、逻辑等价检查（LEC）和物理设计实现。
- 有后硅调试和硅片启动的实际经验。
- 有大型SoC设计、分层DFT流程和多领域集成挑战的相关经验。
- 具备良好的沟通能力，能够独立工作，上手速度快。
查看英文原文
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield
Requirements
Required Skills & Qualifications
- Strong hands-on experience in ASIC DFT with end-to-end ownership.
- Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
- Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation and verification; SMS experience preferred.
- Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
- Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
- Proven post-silicon debug and silicon bring-up experience.
- Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
- Strong communication skills and the ability to work independently with minimal ramp-up.
Originally posted on Himalayas