物理设计工程师 - Synth
Physical Design Engineer - Synth
### **关于 Positron AI**
Positron AI 正在打造下一代 AI 推理加速器，从零开始设计，专为低延迟、高吞吐量的大语言模型推理而生。为训练时代设计的芯片在推理时会遇到两大瓶颈：内存带宽和芯片间网络。我们设计的架构可以突破这两道障碍。我们的第一代 Atlas 系统正在 Oracle Cloud Infrastructure 上部署。Asimov 是我们的首款定制 ASIC，将这一架构转化为硅片。在模拟中，Asimov 的每美元和每瓦特生成的 token 数量是领先 GPU 的数倍，功耗却仅为它们的一小部分。在 Titan 系统中配对使用，Asimov 可以支持超过 16 万亿参数的模型。2026 年 9 月，我们以 50 亿美元估值融资 8.75 亿美元。NEA 领投了此轮融资，Atreides Management、Valor Equity Partners 等其他投资方也参与其中，以推动 Asimov 和 Titan 上市。我们的团队成员来自 Groq、Lambda、NVIDIA、Meta、F5 等多家行业领军企业。
#### 职位概述
我们正在寻找一位高级物理设计工程师 - 综合，负责我们 AI 加速器路线图中关键模块的综合、时序收敛和实现准备。这是一项需要亲力亲为的工程职位，负责将高质量的 RTL 转换为可实现的网表，开发和维护时序约束，并与 RTL 设计师和后端实现合作伙伴紧密合作，推动物理感知优化。你将成为架构、RTL、验证和物理实现之间的关键技术纽带，与高级技术领导一起加强和扩展我们的综合方法。
#### 主要职责
**综合执行与方法论**
- 负责指定模块和子系统的综合，按时交付干净、高质量的网表。
- 参与综合流程的开发和改进，包括约束开发、时序预算、QoR 优化、增量综合和分层实现。
- 协助定义并应用综合交付物的签收标准。
**实际综合与约束开发**
- 使用行业领先的 EDA 工具（如 Cadence Genus 和 Synopsys Design Compiler 或等效工具）进行实际综合。
- 开发和维护 SDC 约束、时钟定义、虚假路径、多周期路径、生成时钟和 MMMC 环境。
- 跟踪并持续提升综合 QoR
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### **About Positron AI**
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
#### Role Overview
We're looking for a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap. This is a hands-on engineering role responsible for turning high-quality RTL into implementation-ready netlists, developing and maintaining timing constraints, and driving physical-aware optimization in close collaboration with RTL designers and backend implementation partners. You will be a key technical link between architecture, RTL, verification, and physical implementation, working alongside senior technical leadership to strengthen and scale our synthesis methodology.
#### Key Responsibilities
**Synthesis Execution & Methodology**
- Own synthesis for assigned partitions and subsystems, delivering clean, high-QoR netlists on schedule.
- Contribute to the development and improvement of synthesis flows, including constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
- Help define and apply signoff criteria for synthesis deliverables.
**Hands-On Synthesis & Constraint Development**
- Run hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
- Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
- Track and continuously improve synthesis QoR for your blocks.
**Timing Closure**
- Drive logical timing closure for assigned partitions, optimizing across frequency, area, power, congestion, and wireability.
- Perform root-cause analysis of timing bottlenecks and contribute to chip-level timing budgets.
- Work with architecture and RTL teams to identify and resolve timing risks before physical implementation.
**Physical-Aware Optimization**
- Partner with backend implementation engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization, and logic restructuring.
- Give RTL teams actionable feedback so designs are implementation-friendly from the outset.
**Cross-Functional Execution**
- Collaborate with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
**Vendor Collaboration**
- Work with external implementation partners to review QoR, timing, and area reports, and support constraint methodology and acceptance criteria.
**AI-Enabled Engineering**
- Apply AI tools to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
#### Required Qualifications
- 8+ years of ASIC implementation experience, including at least two successful tapeouts.
- Strong hands-on proficiency in synthesis and flow development.
- Proven experience closing timing on complex, multi-million-gate designs.
- Deep working knowledge of Cadence Genus and/or Synopsys Design Compiler.
- Strong SDC expertise, including constraint development and MMMC environments.
- A solid grasp of RTL design principles and implementation-friendly coding practices.
- Hands-on experience with advanced process nodes (7nm and below preferred).
- Strong Tcl and Python scripting ability for automation and flow development.
- Excellent debugging and root-cause analysis skills.
#### Preferred Qualifications
- Experience with AI accelerators, CPUs, or GPUs.
- Experience at 5nm and below.
- Familiarity with LPDDR, PCIe, or SerDes interfaces.
- Exposure to chiplet-based architectures and multi-clock SoC designs.
- Experience mentoring junior engineers or leading synthesis for a subsystem.
#### Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. This job description is a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
#### What Success Looks Like
Within one year, this person will have delivered predictable timing closure and high-QoR netlists for their assigned partitions, reduced implementation iterations through strong constraints and early RTL feedback, and made meaningful contributions to a scalable synthesis methodology that supports future ASIC generations.
#### Why Join Us?
- Play a key role in synthesis and timing closure for next-generation AI inference accelerators.
- Work at the cutting edge of AI hardware, directly influencing chips built to power frontier AI workloads.
- Grow your technical scope alongside an experienced, high-caliber implementation team.
#### Compensation & Benefits
The base salary range for this role is **$200,000 – $300,000**.
These figures represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.
#### Benefits & Perks
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
**Health and wellness**
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
**Time off and flexibility**
- Unlimited paid time off — we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
**Compensation and future**
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
#### Visa Support
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
_Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you._