AI芯片，DFT工程师
AI Silicon, DFT Engineer
Unconventional 的使命是解决这个问题。我们从零开始重新思考计算，打造一个效率提升 1000 倍的 AI 新基础。我们通过利用半导体丰富的物理特性，将神经网络直接映射到器件物理，而不是依赖低效的抽象层。
职位描述
作为技术团队成员，DFT 工程师，你将成为我们跨学科研发团队的核心成员。我们寻找在架构与硅片交界处茁壮成长的人才，将创新的 AI 概念转化为高性能、低功耗的硬件。你将负责我们新型计算平台的可测试性实现，确保我们的复杂数字逻辑和定制混合信号模块可以可靠地进行测试。
职责
- DFT 架构与实现：使用行业标准 CAD 工具主导全面测试架构的实现。这包括扫描压缩、内存内置自检（MBIST）和 JTAG/边界扫描逻辑的插入、配置和验证。
- 分层 DFT 实现：推动针对大规模 SoC 设计的自底向上的分层 DFT 方法，管理核心级别的测试封装、模式重定向以及顶层测试集成，以优化运行时间和容量限制。
- 代工厂接口与缺陷分析：主导整体 DFT 策略，紧密配合代工厂接口，分析缺陷密度并推动测试芯片的良率提升。
- 多堆叠芯片 DFT：推动 2.5D/3D 多堆叠芯片封装的前沿 DFT 方法。你将确保通过 IEEE 1838 等新兴标准实现芯片间接口的全面测试覆盖。
- 模拟宏单元 DFT：在数字与模拟设计的交界处工作，促进定制模拟混合信号模块的集成与可测试性。你将为在数字结构中运行的非标准模拟宏单元开发创新测试策略。
- 测试与 PPA 优化：与架构师密切合作，推动激进的测试覆盖率、测试时间和良率目标。
查看英文原文
About Unconventional
Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.
At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.
The Role
As a Member of Technical Staff, DFT Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the testability realization of our novel computing platform, ensuring that our complex digital logic and custom mixed-signal blocks can be reliably tested.
Responsibilities
- DFT Architecture & Implementation: Lead the implementation of comprehensive test architectures using industry-standard CAD tools. This includes the insertion, configuration, and verification of scan compression, Memory Built-In Self-Test (MBIST), and JTAG/boundary scan logic.
- Hierarchical DFT Implementation: Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs, managing core-level test wrapping, pattern retargeting, and top-level test integration to optimize runtime and capacity limits.
- Foundry Interface & Defect Analysis: Own the overarching DFT strategy, working closely with foundry interfaces to analyze defect densities and drive yield improvements for test chips.
- Multi-Stacked Die DFT: Drive cutting-edge DFT methodologies for 2.5D/3D multi-stacked die packaging. You will ensure comprehensive test coverage across die-to-die interfaces utilizing emerging standards like IEEE 1838.
- Analog Macro DFT: Work at the interface of digital and analog design to facilitate the integration and testability of custom analog mixed-signal blocks. You will develop novel test strategies for non-standard analog macros operating within the digital fabric.
- Test & PPA Optimization: Drive aggressive test coverage, test time, and yield targets while working closely with architects to influence the micro-architecture for better Power, Performance, and Area (PPA).
- Sign-off & Verification: Own the final DFT sign-off process. This includes Automatic Test Pattern Generation (ATPG), test vector validation, fault simulation, and ensuring clean timing closure during Static Timing Analysis (STA) for all test modes.
- Methodology Development: Contribute to the development and automation of our design flow. Set best practices for testability to ensure first-pass silicon success.
- Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency.
Minimum Qualifications
- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 10+ years of industry experience in digital DFT and test architecture, with a track record of successful tapeouts on modern process nodes (7nm, 5nm, or newer preferred).
- Technical Expertise:
- Deep expertise in scan compression, MBIST generation, fault modeling (stuck-at, transition, path delay), and ATPG.
- Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation) and their impact on test reliability.
- Expertise in Static Timing Analysis (STA) and timing closure for complex designs in shift and capture test modes.
- Design Flow Proficiency:
- Expert-level mastery of standard EDA CAD tool suites for DFT implementation and vector generation.
- Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
- Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.
Preferred Qualifications (Nice to Have)
- Advanced Packaging Test: Hands-on experience with modern die-to-die (D2D) interconnect test strategies, chiplet testing, and 3D-IC DFT architectures.
- Custom AI Hardware: Experience with test architecture for Machine Learning accelerators or large-scale systolic arrays.
- Mixed-Signal Integration: Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
- AI Tools: Familiarity with state of the art AI tools to accelerate chip design.
Why Join Us?
- The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
- The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
- The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.
- The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Mountain View office.
Originally posted on Himalayas