Senior ASIC Physical Design Engineer
尼奥比米微系统开发高性能微电子产品，以实现安全收集，处理和分布关键数据。我们是政府研究团队和商业客户的可靠合作伙伴，其解决方案需要更低功率，更高效率和已证明的安全性。我们的团队作为2021年由全球级安全和计算系统研发公司 Galois Inc 创立，该团队结合了几十年的先进半导体设计经验与提供世界级解决方案的记录。关于这个角色 我们正在寻找一个经验丰富的 ASIC 物理设计，以从 RTL 交付到带状传输来推动复杂 SoC 设计的实施。理想候选人拥有8年以上先进节点实体实现的实践经验，多个成功的带状传递的证明所有权和技术上和组织上领导的能力。在这个角色中，你将与建筑，RTL 设计，验证，DFT 和电力团队密切合作，在尖端技术节点提供高性能，高效的。责任作为物理设计，你将负责：终端实体实施领导 · 拥有和领导所有物理设计活动，从 RTL 交付，地板规划和 PNR 到最终 GDSII 的交付。· 为整个物理设计流程定义执行策略，时间表，设计方法及质量检查点。地板规劃与 SoC 集成 ·为大型层次式 SoC 构建并执行地板规定的战略，包括：· IP 集成和宏观配置 ·物理分区和层次定义 ·电网架构和时钟分布拓 · DIE 大小，面积比率和物理限制 · 与建筑和 RTL 团队合作以确保物理可行性，定制关闭准备以及区域/功率目标。位置和路线+时间关闭 · 使用行业标准的 EDA 工具 (Cadence, Synopsys) 的领导块级和顶级 PNR. · 在角落，模式，电压域和操作条件中驱动时机融合。· 自主优化 PPA （功率，性能，区域）,堵塞减轻和物理完整性。钟表，电源和停电 ·实现 CTS 和驱动偏差，延迟和钟表功率优化。·引领 IR/EM 信号退出策略，热分析以及全芯片物理验证 (DRC/LVS/ERC). ·集成和 val.
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About Niobium
At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.
Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.
About This Role
We are seeking a highly experienced ASIC Physical Design to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 8+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.
In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.
Responsibilities
As the Physical Design Lead, you will be responsible for:
End-to-End Physical Implementation Leadership
- Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.
- Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.
Floorplanning & SoC Integration
- Architect and execute floorplanning strategies for large, hierarchical SoCs, including:
- IP integration and macro placement
- Physical partitioning and hierarchy definition
- Power grid architecture and clock distribution topology
- DIE size, aspect ratio, and physical constraints
- Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.
Place & Route + Timing Closure
- Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).
- Drive timing convergence across corners, modes, voltage domains, and operating conditions.
- Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.
Clocking, Power, and Sign-Off
- Implement CTS and drive skew, latency, and clock power optimization.
- Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).
- Integrate and validate low power methodologies, including UPF/CPF flows.
Cross-Functional Collaboration & Quality Ownership
- Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
- Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
- Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.
Leadership & Mentorship
- Provide technical leadership to a team of junior and mid-level physical designers.
- Mentor, coach, and guide engineers in methodology, debug, and best practices.
- Champion continuous improvement across flows, scripts, and design methodology.
Key Qualifications
Education
· BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
(Advanced degree preferred for leadership roles.)
Required Technical Expertise
- 8+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape-outs at advanced technology nodes (16nm → 3nm preferred).
- Deep expertise in:
- Floorplanning
- Place & Route
- CTS
- STA/Timing Closure
- Physical verification & sign-off
- Low power design and UPF
- Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
- Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.
- Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
Required General Skills
- Strong communication skills—able to articulate technical decisions across cross-functional teams.
- Highly motivated, proactive, and able to operate effectively in a distributed team environment.
- Comfortable owning schedules, deliverables, and quality in a fast-moving development cycle.
- Exceptional analytical, debugging, and problem-solving skills with a meticulous attention to detail.
Location
Niobium is headquartered in Columbus, Ohio with additional locations in Fayetteville, Arkansas, Portland, Oregon, and Dayton, Ohio. We will not be limited by geography for the right candidate.
Benefits
Niobium offers a highly competitive benefits program to support employees and their families, including:
- Competitive salaries
- Equity in the form of Incentive Stock Options (ISO)
- Employer paid medical insurance plan
- Health Savings Account (HSA) with employer contributions
- Dental and vision reimbursement account (HRA)
- 401(k) retirement plan with employer match
- Flexible work location with remote options
- Flexible time off
Originally posted on Himalayas