可测性设计（DFT）工程师
Design for Test (DFT) Engineer
**关于 Positron AI**
Positron AI 专注于开发定制的硬件系统，以加速 AI 推理。这些推理系统在性能和效率方面相比传统的 GPU 系统有显著提升，在每美元性能和每瓦性能方面都有优势。Positron 的目标是打造世界上最优秀的 AI 推理系统。
**职位概述**
Positron AI 正在构建下一代 AI 推理加速器，从我们的首款 ASIC Asimov 开始，还有更多代产品正在开发中。作为首席 DFT 工程师，您将全面负责 DFT 和 DFx 策略：定义加速器的 DFT 架构，将其集成到内部 RTL 和第三方 IP 中，与后端设计合作伙伴合作推动实现，并通过全面的预硅验证确保高质量的芯片启动。这是一个从架构到流片再到首颗芯片的全栈技术主导角色，而非协调角色。
**主要职责**
**负责 Positron 的 DFT 策略**
- 定义并维护 Asimov 及未来 ASIC 产品的 DFT 架构。
- 制定与产品质量、制造、良率、诊断和可靠性目标一致的长期 DFT 和 DFx 路线图。
- 在整个工程组织中建立 DFT 设计标准、评审流程、签收标准和最佳实践。
**实际的 DFT 实现**
- 设计和实现扫描插入、压缩、ATPG、内存 BIST、逻辑 BIST（适当情况下）、边界扫描 / IEEE 1149.x、IJTAG / IEEE 1687 基础设施以及调试/可观测性功能。
- 将 DFT 集成到内部开发的 RTL 中。
- 评估并集成第三方 IP 供应商提供的 DFT 功能。
- 直接参与 RTL、综合和 DFT 工具流程。
**推动预硅 DFT 验证**
- 制定全面的 DFT 验证计划。
- 通过仿真和门级验证验证 DFT 功能。
- 在流片前确保结构覆盖率目标达成。
- 推动 DDA、固定故障、转换、单元感知和电源感知的 ATPG 策略。
- 负责 DFT 签收。
**与物理设计团队合作**
- 与后端实现团队紧密合作，确保 DFT 架构的物理实现成功。
- 指导扫描链分割、压缩规划和测试时钟架构。
- 解决电源感知的测试实现、时序闭合考虑因素和测试模式集成。
**负责外部 DFT 执行**
查看英文原文
**About Positron AI**
Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
### **Role Overview**
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.
### **Key Responsibilities**
**Hands-on DFT Implementation**
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
- Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
**Drive Pre-Silicon DFT Verification**
- Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
- Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
**Partner with Physical Design**
- Work closely with backend implementation teams to ensure successful physical realization of the DFT architecture.
- Guide scan chain partitioning, compression planning, and test clock architecture.
- Address power-aware test implementation, timing closure considerations, and test mode integration.
**Cross-Functional Execution**
- Partner closely with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.
**AI-Enabled Engineering**
- Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
### **Required Qualifications**
- A BS, MS, or PhD in Electrical Engineering or Computer Engineering.
- 8+ years of ASIC development experience.
- Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts.
- Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis.
- Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required.
- Strong RTL design skills using Verilog/SystemVerilog.
- Practical experience with synthesis and gate-level verification.
- Strong scripting ability in Python, Tcl, Perl, or similar languages.
- Excellent debugging skills across RTL, netlists, and silicon failure analysis.
- A demonstrated ability to drive technical execution across cross-functional engineering teams.
### **Preferred Qualifications**
- Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.
- Exposure to high-speed SerDes and advanced process nodes (5nm and below).
- Background in low-power design, yield enhancement methodologies, and manufacturing test optimization.
- Hands-on experience with silicon bring-up, failure analysis, and post-silicon debug.
- A solid grasp of secure manufacturing and DFT, including the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test.
- Experience architecting in-system debug and observability infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up.
- Familiarity with emulation and pre-silicon validation platforms such as Palladium, ZeBu, Veloce, or FPGA prototyping to validate DFT features before tapeout.
#### **Leveling & Scope**
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
### **Why Join Us?**
- Own DFT for a purpose-built AI inference accelerator from architecture definition through first silicon, with your decisions shaping Asimov and every generation that follows.
- Join a small, senior hardware team where your work directly determines silicon quality, yield, and time to market for frontier AI workloads.
### **Compensation & Benefits**
The base salary range for this role is $200,000 – $300,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
### **Benefits & Perks**
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
**Health and wellness**
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
**Time off and flexibility**
- Unlimited paid time off; we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
**Compensation and future**
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
### **Visa Support**
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
**Equal Opportunity Employer.** If you're excited about the role but don't meet every bullet, we'd still love to hear from you.