Front End RTL Designer / SoC integration
关于我们：AI 计算正在打击一个硬的物理墙，内存瓶正在压倒整个行业。成立于2024年10月并获得570万欧元资金，垂直计算通过专有的垂直集成记忆 (VIMTM) 芯片解决这一问题，使人工智能硬件更快，绿色和更可扩展。我们是一个跨学科团队将突破性半导体物理学转化为商业现实。为什么？:现在，18个月的密集研发后，垂直计算机已经达到关键的拐点。我们的基础技术已得到验证，并且我们成功地实现了核心技术里程碑。凭借经过验证的技术数据包和持续系统研究，我们现在从纯粹的研发转向与全球企业客户积极参与。随着我们在2027年开始准备下一阶段规模和增长时，今天加入我们意味着直接拥有将推动 AI 计算的下一个时代的硬件基础。关于角色：我们正在寻找前端 RTL 设计师来为构建我们的垂直计算3D 集成芯片做出贡献。在这个职位中，你将专注于顶级一体化和整合所有 IP 以构建 AI 加速器，该加速器将展示我们的垂直集成内存 (VIMTM) 技术的全部潜力。你将处理完整的 SoC 集成，与验证和物理设计团队密切合作以确保产品的目标功率，性能和区域 (PPA). 主要责任：·领导顶级 SoC 和芯片集成，并结合所有内部和第三方 IP 来构建高性能 AI 加速器。· 将专有垂直集成内存 (VIMTM) 技术与计算引擎集成，以最大化吞吐量和带宽效率。· 与功能验证团队紧密合作，建立验证环境，调试 RTL 问题，并确保强大的设计覆盖。· 与物理设计团队合作，优化功率，性能和区域 (PPA),支持合成，时间关闭和地板规划。关于团队：这个角色是硬件 (HW) 团队的一部分，直接向 HW 经理报告。你将加入一个致力于提供尖端的 AI 加速器解决方案并推进内存和计算集成界限的协作创新团队。你的要求：· 在前端 RTL 设计和顶级 SoC/chiplet 集成方面具有坚实的背景和经验。·
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About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a Front-End RTL Designer to contribute to building our Vertical Compute's 3D-integrated chiplets. In this role, you will focus on top-level integration and integrating all IPs to build the AI accelerator that will demonstrate the full potential of our Vertical Integrated Memory (VIM™) technology. You will handle full SoC integration, working in close collaboration with verification and physical design teams to ensure the targeted Power, Performance, and Area (PPA) of the product.
Key Responsibilities:
- Lead top-level SoC and chiplet integration, incorporating all internal and third-party IPs to build high-performance AI accelerators.
- Integrate proprietary Vertical Integrated Memory (VIM™) technology with compute engines to maximize throughput and bandwidth efficiency.
- Partner closely with functional verification teams to build verification environments, debug RTL issues, and ensure robust design coverage.
- Collaborate with physical design teams to optimize Power, Performance, and Area (PPA), supporting synthesis, timing closure, and floorplanning.
About the team:
This role is part of the Hardware (HW) team, reporting directly to the HW Manager. You will join a collaborative and innovative team dedicated to delivering cutting-edge AI accelerator solutions and pushing the boundaries of memory and compute integration.
Requirements
About who you are:
- Solid background and experience in front-end RTL design and top-level SoC/chiplet integration.
- Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
- Strong hard skills in RTL languages (SystemVerilog/Verilog), IP integration, and working closely with verification and physical design teams to optimize PPA (Power, Performance, Area).
- Strong communication and collaborative problem-solving skills in a fast-paced environment.
- Fluency in English with effective written and verbal communication skills.
Highlights
Leading and mentoring engineering teams, managing projects from concept to silicon qualification, and collaborating with key industry partners to deliver innovative memory solutions.
Originally posted on Himalayas