Asics Engineer
要求请参阅项目描述中以下关键词。SCAN,ATPG,MBIST,时机模拟，SDF,SDC ,PSV,诊断，模式重定位，模式移植，DRCs,TetraMax,DFTMax 经验10年以上的 ASIC 设计为测试 (DFT) 角色摘要 我们正在寻找一个具有高度经验的领导 ASIC DFT 工程师来构建，实施，验证和调整复杂 ASIC 和 SoC 设计的先进 DFT 解决方案。这一职位需要深入的技术知识，包括 DFT 架构，扫描插入，ATPG,MBIST/LBIST,JTAG,边界扫描和后验证，以及领导跨功能调试工作并推动关键问题的解决能力。理想候选人将拥有强大的实践专业知识在 DFT 基础上，故障模型，测试覆盖，诊断和调试，以及评估和采用新兴 DFT 方法及建筑方案来提高稳定性，质量和产能。重点责任 · DFT 架构；实施，验证和复杂 ASIC 和 SoC 设计的首席签名。· 驱动扫描架构，扫描插入，扫描链接和扫描压缩工作流程以实现高覆盖率和强大的可测度。· 在设计和带来阶段内拥有 MBIST/LBIST 集成，实施，验证和调试。· 对复杂的问题进行 DFT 调试，故障分析，根源调查和漏洞覆盖关闭。·开发并验证包括 DFT SDC,时间检查和 DFT 特定时间分析在内的 DFT 限制。·与 RTL 设计，验证，物理设计，STA 和验证团队合作解决集成和执行问题的问题。· 支持 ATPG 模式生成，ATPG 模拟，DRC 分析，测试覆盖面分析和诊断/调整。· 在 JTAG,边界扫描，iJTAG ,SSN 和 IP 级 DFT 集成工作。· 对 RTL,合成，LEC 以及物理设计对 DFT 实施和测试质量的影响进行审查。·作为先进的 DFT 和后调整问题的技术升级点。· 导师初级和中级 DFT 工程师并促进 DFT 方法学和自动化最佳实践。·使用 TCL,PERL 或 Python 开发脚本和自动化的程序以提高流程效率和调整生产力。所需技能和资格 ·具有端到端所有权的 ASIC DFT 强有实践经验。· 充分了解 DFT
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Requirements
please see these key words of in the project description for the profile consideration.
“SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax “
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
- Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
- Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
- Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
- Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
- Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
- Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
- Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
- Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
- Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
- Act as a technical escalation point for advanced DFT and post-silicon debug issues.
- Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
- Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
- Strong hands-on experience in ASIC DFT with end-to-end ownership.
- Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
- Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation and verification; SMS experience preferred.
- Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
- Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
- Proven post-silicon debug and silicon bring-up experience.
- Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
- Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
- MBIST post-silicon validation.
- ATPG simulations and fault coverage debug.
- DFT RTL, DFD, DFT verification, and IP-level DFT integration.
- DFT SDC creation and DFT timing closure support.
- Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
- TCL/PERL scripting for DFT automation, reporting, and debug.
- Experience working across multiple ASIC technology nodes and complex product development cycles.
- Familiarity with yield learning, diagnosis, and manufacturing test optimization.
Originally posted on Himalayas