Design for Test Engineers
公司概述 Tessolve 提供了预和后专业知识的独特组合，以提供 VLSI 设计，测试 &产品工程和嵌入式系统的端到端解决方案。我们与全球领先的半导体公司合作，通过深层领域知识和工程卓越实现创新。角色总结 我们正在寻找有技能和动机的测试设计 (DFT) 工程师，拥有410年的经验在开发和实施复杂 SoC 和 ASIC 的高级 DFT 方法。关键责任 ·为 SoC/ASIC 设计制定和实施 DFT 架构。· 利用扫描插入，ATPG,MBIST,LBIST,JTAG 和边界扫描方面的专业知识。· 为 Synopsys/Mentor/Cadence DFT 工具开发工具流程工作。· 与 RTL,物理设计，验证和测试团队合作整合并验证 DFT 功能。· 在合成，模拟和化过程中调试和解决问题。·同时优化面积，功率和性能模式的测试覆盖性提供高质量。·支持 ATE 生成和验证模式。所需资格 ·必须有：·对 DFT 方法 （扫描，ATPG ,BIST,边界扫码，JTA G,压缩技术）的强大的了解。·实践经验与行业标准的 DFT EDA 工具 (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent). ·对 RTL 设计，逻辑合成，时间和验证的良好理解。·在前和后阶段进行固定的调试和解决问题技能。·处理复杂的 SoC/ASIC 设计，具有数百万门的操作经验。·自动化编写技巧 (Perl,Python,TCL,Shell). ·优秀的沟通和团队合作能力。· 拥有：·电子/电气/计算机工程或相关领域学士学位。·接触低功率 DFT 技术和高级节点 (7/5/3nmnm). · ATE 测试的经验，生产测试支持。薪酬和福利 ·竞争性工资和基于绩效的奖励。· 健康，牙科和视力保险。·与雇主匹配的退休计划。·有偿假期和假期假期。·持续培训和专业发展机会。额外信息 · 本职位是工程部门的一部分，成功的候选人将向 DFT 工程管理员报告。·本职位可供应：1.最初发布在喜马拉雅山。
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Company Overview
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide end-to-end solutions in VLSI Design, Test & Product Engineering, and Embedded Systems. We work with leading semiconductor companies worldwide, enabling innovation through deep domain knowledge and engineering excellence.
Summary of the Role
We are looking for skilled and motivated Design for Test (DFT) Engineers with 4–10 years of experience in developing and implementing advanced DFT methodologies for complex SoCs and ASICs.
Key Responsibilities
- Develop and implement DFT architectures for SoC/ASIC designs.
- Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan.
- Work on tool flows for Synopsys/Mentor/Cadence DFT tools.
- Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features.
- Debug and resolve issues during synthesis, simulation, and silicon bring-up.
- Deliver high-quality test coverage while optimizing for area, power, and performance impact.
- Support ATE patterns generation and silicon validation.
Required Qualifications
- Must-Have:
- Strong knowledge of DFT methodologies (Scan, ATPG, BIST, Boundary Scan, JTAG, compression techniques).
- Hands-on experience with industry-standard DFT EDA tools (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent).
- Good understanding of RTL design, logic synthesis, timing, and verification.
- Solid debugging and problem-solving skills across pre-silicon and post-silicon phases.
- Experience in handling complex SoC/ASIC designs with multi-million gates.
- Scripting skills (Perl, Python, Tcl, Shell) for automation.
- Excellent communication and teamwork skills.
- Nice-to-Have:
- Bachelor’s/Master’s degree in Electronics/Electrical/Computer Engineering or related field.
- Exposure to low-power DFT techniques and advanced nodes (7nm/5nm/3nm).
- Experience in ATE test bring-up and production test support.
Compensation and Benefits
- Competitive salary and performance-based bonuses.
- Health, dental, and vision insurance.
- Retirement plan with employer matching.
- Paid time off and holiday leave.
- Ongoing training and professional development opportunities.
Additional Information
- This position is part of the engineering department, and the successful candidate will report to the DFT Engineering Manager.
- Openings available for this role: 1.
Originally posted on Himalayas