高级验证工程师
Senior Verification Engineer
在TechBiz Global，我们为我们的顶级客户提供建筑服务。我们目前正在寻找一名高级验证工程师加入一家开发RISC-V CPU核心的客户的团队。如果您正在寻找一个在创新环境中成长的 exciting 机会，这可能是您的完美选择。
作为高级验证工程师，您将加入验证团队，并在根据规范使用先进的验证方法和工具来验证设计时，发挥关键作用，确保复杂数字设计在寄存器传输级别上的正确性和功能性。
要求
- 硕士或博士学历
- 英语C1水平
- 8年以上工业经验
- 精通SystemVerilog和UVM
- 熟悉脚本语言（Python、Perl、Bash、TCL）和回归工具
- 有仿真和仿真工具的经验
- 熟悉版本控制方法和工具（git、svn）
- 有模块级和子系统或顶层验证的经验
- 有形式化和动态验证的经验
- 强大的问题解决能力和细致入微的注意力
- 优秀的沟通和团队合作能力
亮点
- 需要流利的英语
最初发布于Himalayas
查看英文原文
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking an Senior Verification Engineerspecialist to join one of our clients' teams that develops RISC-V CPU cores. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.
As a Senior Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.
Requirements
- Master or PhD
- English C1
- Industrial experience +8 years
- Proficiency in SystemVerilog and UVM
- Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and sub-system or top level verification
- Experience with formal and dynamic verification
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities
Highlights
-fluent English is required
Originally posted on Himalayas