模拟混合信号电路设计工程师
Analog Mixed-Signal Circuit Design Engineer
Ferric, Inc. 简介
Ferric 是一家位于纽约市的技术初创公司，正在开创一种全新的集成电路和电子组件供电方式。这种方法利用 Ferric 将薄膜磁性电感器与 CMOS 技术相结合，相比目前市面上的现有技术，显著提升了电压调节器（VR）的集成密度和效率。
作为 Ferric 的设计工程师，你将参与开发最先进的集成电压调节器，利用 Ferric 在片上电感器技术方面的行业领先优势。这些产品应用范围广泛，从高功率现代 SoC 到超低功耗移动平台，包括可穿戴设备。
主要职责：
- 设计模拟和混合信号电路，满足不同 CMOS 工艺节点的架构要求和技术规范
- 积极参与设计架构定义和芯片集成工作，并与业务和应用团队合作，定义新一代 IC 的规格
- 研究和探索新的电路技术，以帮助提升 Ferric IC 的性能
- 执行分析、设计和验证仿真，确保构建模块在原理图级别和布局后提取后均符合规范
- 文档化所负责的模块，组织设计评审会议并参与评审
- 与表征、测试和应用工程师跨职能协作，验证、表征和调试所负责的电路模块
最低要求：
- 博士或硕士学历，电子工程专业，2年以上全定制 CMOS 设计经验
- 具备带隙基准、ADC/DAC、PLL/DLL、LDO、温度传感器、开关电容电路、运算放大器、比较器和偏置电路等领域的设计技能
- CAD 软件：Cadence Virtuoso 原理图和版图、Spectre、APS、Calibre DRC/LVS/PEX、CppSim
优先考虑：
- 在标准 CMOS 工艺中设计高开关频率集成电压调节器的经验
- 在标准 CMOS 工艺中设计模拟和混合信号电路的经验，尤其注重低功耗设计
- 有将混合信号设计带入大批量生产的成功记录
- 对工艺和器件物理概念有深入理解
- 熟悉混合信号验证方法
- 能够布局关键的模拟和混合信号电路
- 具有后端验证经验
查看英文原文
About Ferric, Inc.
Ferric is a technology startup based in New York City that is pioneering an entirely new approach to power delivery for Integrated Circuits and Electronic Assemblies. This approach leverages Ferric’s integration of thin-film magnetic inductors with CMOS technology to enable a significant improvement in the integration density and efficiency of voltage regulators (VRs) compared with current commercially available technologies.
As a Ferric Design Engineer, you contribute to building the most advanced cutting edge integrated voltage regulators, leveraging Ferric’s industry-leading on-chip inductor technology. These products have applications ranging from high-power modern SoCs to ultra-low power Mobile platforms including wearable devices.
Primary Responsibilities:
- Design analog and mixed-signal circuits meeting architectural requirements and technical specifications in various CMOS nodescad
- Actively contribute to the architectural definition of the design and chip integration and work with business and application team to define specifications for upcoming IC's
- Research and investigate new circuit techniques to help improve Ferric IC's
- Perform analysis, design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction
- Document assigned blocks, and hold design review meetings and participate in the reviews
- Work cross-functionally with Characterization, Test, and Application Engineers to verify, characterize and debug owned circuit blocks
Minimum Qualifications:
- PhD or MSEE with 2+ years of experience in full-custom CMOS design
- Design skills in areas such as bandgaps, ADC's/DAC's, PLL's, DLL's, LDO's, temperature sensors, switched-capacitor circuits, op-amps, comparators, and biasing circuits.
- CAD Software: Cadence Virtuoso Schematic and Layout, Spectre, APS, Calibre DRC/LVS/PEX, CppSim
Preferred Qualifications:
- Experience designing high switching frequency integrated voltage regulators in standard CMOS technologies
- Experience designing analog and mixed-signal circuits in standard CMOS technologies with an emphasis on low-power consumption
- Proven track record for bringing mixed-signal designs into high volume production
- Deep understanding of process and device physics concepts
- Familiarity with mixed signal verification methodologies
- Ability to layout critical analog and mixed-signal circuits
- Experience with backend verification tools including EMIR, static/dynamic MOSFET voltage checks, etc
- Experience with Monte Carlo analysis
- Languages: Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB
Desired Characteristics & Attributes:
- Passionate, self-starter with strong commitment to flawless execution
- Excellent written and verbal communication skills required
- Ability to work well with others in a fast-paced collaborative team environment
Logistics:
- Remote or in NYC office
- Annual salary range for this position 115k-170k
Originally posted on Himalayas