高级模拟 IC 设计工程师 - IVR 架构团队
Sr. Analog IC Design Engineer - IVR Architecture Team
关于 Ferric, Inc.
Ferric 是一家位于纽约市的技术初创公司，正在开创一种全新的集成电路和电子组件供电方式。这种方法利用 Ferric 将薄膜磁性电感器与 CMOS 技术相结合，与目前市面上的现有技术相比，显著提升了电压调节器（VR）的集成密度和效率。
作为 Ferric 模拟 IC 设计工程师，你将参与构建最先进的集成电压调节器，利用 Ferric 先进的片上电感器技术。这些产品应用范围广泛，从千瓦级的人工智能处理器到超低功耗的移动平台，包括可穿戴设备。
你的主要职责包括负责系统架构，定义系统子模块的规格，并确保系统设计满足产品目标要求。
主要职责：
- 驱动系统架构设计，以优化 Ferric IVR 的产品性能目标，如效率、密度、负载电流瞬态响应、输入电源抑制和参考跟踪性能。
- 根据系统级需求，确定系统内各子模块的规格。
- 维护并实现各种类型的系统级模型，以探索创新的电源转换和控制解决方案。
- 进行系统级仿真和验证，重点关注通过实验台对比进行性能预测。
- 按需设计、仿真和布局与 IVR 相关的模拟 IP。
- 在设计、应用和测试团队之间推动系统级性能目标，以确保最佳结果。
最低要求：
- 电子工程硕士（MSEE）学历，具有模拟设计经验。
- 精通控制理论和稳定性分析。
- 精通开关电源转换器设计。
- 深入了解 CMOS 模拟电路设计，具备数字电路设计知识。
- 具有定制 IC 设计流程和工具的经验。
优先考虑：
- 本科电子工程（BSEE）+ 8 年，硕士（MSEE）+ 5 年，或博士（PhD）+ 2 年在电源或射频 IC 设计或相关领域的经验。对于超出此范围但表现出色的候选人，也可能被考虑。
- 具有设计高开关频率集成电压调节器的经验。
- 具有在标准 CMOS 中设计 IC 的经验。具备特殊半导体经验者优先。
- 深入理解
查看英文原文
About Ferric, Inc.
Ferric is a technology startup based in New York City that is pioneering an entirely new approach to power delivery for Integrated Circuits and Electronic Assemblies. This approach leverages Ferric’s integration of thin-film magnetic inductors with CMOS technology to enable a significant improvement in the integration density and efficiency of voltage regulators (VRs) compared with current commercially available technologies.
As a Ferric Analog IC Design Engineer on the IVR Architecture Team, you contribute to building the most advanced cutting edge integrated voltage regulators, leveraging Ferric’s industry-leading on-chip inductor technology. These products have applications ranging from KW-scale AI processors to ultra-low power Mobile platforms including wearable devices.
Your primary responsibilities include ownership of system architectures, defining specifications for system sub-blocks, and ensuring that the system design meets product target requirements.
Primary Responsibilities:
- Drive system architecture design to optimize product performance targets such as efficiency, density, load current transient response, input supply rejection, and reference tracking performance for Ferric IVRs.
- Identify specifications for sub-blocks within the overall system given system level requirements.
- Maintain and implement various types of system-level models to pioneer novel power conversion and control solutions.
- Perform system-level simulations and verification with a focus on performance prediction through bench correlation.
- Design, simulation, and layout of analog IPs pertinent to IVRs as needed.
- Champion system level performance goals across design, applications, and testing teams to ensure optimal results.
Minimum Qualifications:
- MSEE with analog design experience.
- Strong knowledge of control theory and stability analysis.
- Strong knowledge of switching power converter design.
- Deep knowledge of CMOS analog circuit design, knowledge of digital circuit design.
- Experience with custom IC design flows and tools.
Preferred Qualifications:
- BSEE + 8 years, MSEE + 5 years, or PhD + 2 years experience in power or RF IC design, or related field. Candidates demonstrating exceptional competency outside these ranges may be considered.
- Experience designing high switching frequency integrated voltage regulators.
- Experience designing ICs in standard CMOS. Exotic semiconductors are a plus.
- Deep understanding of process and device physics concepts.
- Familiarity with mixed signal verification methodologies.
- Experience with Monte Carlo analysis.
- Familiarity with analog design EDA tools such as Cadence Virtuoso, schematic capture, LVS, DRC, SPICE simulation, parasitic extraction, electromagnetics simulators.
- Experience with bench-level validation, characterization, and debug of full ICs and IC sub-systems.
- Languages: Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB, etc.
Desired Characteristics & Attributes:
- Passionate, self-starter with strong commitment to relentless execution
- Excellent written and verbal communication skills required
- Ability and desire to proactively steer and coordinate design activities across a multidisciplinary design team.
Location:
- New York, NY
Logistics:
- Remote or in NYC office
- Annual salary range for this position $135,000-170,000
Originally posted on Himalayas