一致性验证工程师
Coherency Verification Engineer
开发工程未标注地域
公司TechBiz Global
薪资未公开
工作地点Worldwide
地域资格未标注地域
时区要求日间重叠约 9 小时，基本正常作息
用工类型Full Time
发布时间今天
数据来源Himalayas
在 TechBiz Global，我们为我们的顶级客户提供建筑服务。我们正在寻找一名一致性验证工程师加入其中一家客户的团队。如果您正在寻找一个在创新环境中成长的激动人心的机会，这可能是您的理想选择
职责：
- 根据架构和设计规范，在 RTL 层次验证复杂的数字设计
- 使用 SystemVerilog 和 UVM 开发和维护验证环境
- 为模块级、子系统级和顶层验证创建、执行和调试测试计划
- 参与一致系统验证，包括缓存相关功能和互连行为
- 验证涉及 CHI 协议、缓存结构、一致性机制和系统级交互的设计
- 使用行业标准验证工具运行和管理仿真、回归测试，并调试失败
- 应用形式化和动态验证方法，尽早发现设计问题
- 使用 Python、Perl、Bash 或 TCL 等脚本语言自动化验证流程和回归测试
- 与架构、设计和验证团队紧密合作，分析规格，明确需求，解决问题
- 跟踪、记录并沟通验证进度、缺陷、覆盖率状态和技术风险
- 为验证方法、工具和最佳实践的持续改进做出贡献
要求
- 硕士或博士学历
- 英语 C1 水平
- 8 年以上工业经验
- 精通 SystemVerilog 和 UVM
- 熟悉脚本语言（Python、Perl、Bash、TCL）和回归测试工具
- 有仿真和仿真工具的经验
- 熟悉版本控制方法和工具（git、svn）
- 有模块级和子系统或顶层验证经验
- 有形式化和动态验证经验
- 强大的问题解决能力和细致的工作态度
- 优秀的沟通和团队合作能力
- 熟悉 CHI 协议
- 了解缓存结构和参数
- 有统一系统验证经验
最初发布于 Himalayas
查看英文原文
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Coherency Verification Engineer to join one of our clients' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.
Responsibilities:
- Verify complex digital designs at RTL level according to architecture and design specifications.
- Develop and maintain verification environments using SystemVerilog and UVM.
- Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.
- Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.
- Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.
- Run and manage simulations, regressions, and debug failures using industry-standard verification tools.
- Apply both formal and dynamic verification methodologies to identify design issues early.
- Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.
- Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.
- Track, document, and communicate verification progress, bugs, coverage status, and technical risks.
- Contribute to continuous improvement of verification methodology, tools, and best practices.
Requirements
- Master or PhD
- English C1
- Industrial experience +8 years
- Proficiency in SystemVerilog and UVM
- Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and sub-system or top level verification
- Experience with formal and dynamic verification
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities
- Knowledge of the CHI protocol
- Understanding of caches' structure and parameters
- Experience in verification of coherent systems
Originally posted on Himalayas
本页面信息整理自 Himalayas，版权归原发布方所有。职位可能随时关闭，投递请以原始页面为准。
本站只做信息聚合展示，不参与招聘流程，也不向求职者收取任何费用。