Senior Layout Engineer
作为高速连接的全球领导者，Ciena 致力于以人为首的方式。我们的团队享有着重视灵活工作环境优先考虑的文化，使个人增长，幸福感和归属成为最重要的因素。我们是一个技术公司，通过人类来带领我们的业务优先事项，同时推动社会，社区和社会的意义.Ciena 的 Wavelogic 产品通过集成式模拟技术推进高速度光纤传输。这位模拟布局工程师的角色为深微 CMOS 和 BiCMOS 技术中高级高速模拟电路提供了贡献，包括 DAC,ADC,SERDES,跨阻力放大器，调制驱动程序以及精确控制和监控电路。该角色提供高性能模拟布景，从而实现宽带光纤调节机器解决方案。你将如何产生影响：· 评估与高级模拟设计人员合作的模拟电池设计的布局可行性，考虑设计交易和团队输入。·通过地板规划，放置和路由来创建分配的模拟块的布局。· 进行 DRC,ANT,LVS,PERC,EM 和 IR 验证检查以确认布局质量。· 研究可以提高生产力的布局工具和流程功能。·定期提供状态更新，参加团队会议并与组分享知识。必须有：· 教育：电气工程或相关领域学士学位。·经验：5年以上相关行业经验。·使用深微子 CMOS 设备的定制模拟和混合信号布局设计，包括 FinFET 晶体管。·在现有的团队环境中协作以及对团队活动应用建设性方法。·与跨功能团队合作应用的沟通和人际技能。· 基于模拟和混合信号设计，包括 ADC,DAC,PLL 和 SERDES 的定制布局设计。· 使用行业标准布局工具，包括 Cadence Virtuoso,西门子利伯和安赛斯托特姆以及对先进技术节点进行布局设计流程的应用。作为一个平等机会雇主，包括：
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As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Ciena's Wavelogic products advance high-speed optical fiber transmission through integrated analog technologies. This Analog Layout Engineer role contributes to advanced high-speed analog circuits in deep-submicron CMOS and BiCMOS technologies, including DAC, ADC, SERDES, transimpedance amplifier, modulator driver, and precision control and monitoring circuits. The role delivers high-performance analog layouts that enable broadband fiber-optic modem solutions.
How you will make an impact:
- Evaluate layout feasibility for circuit designs in collaboration with senior analog designers, considering design trade-offs and team input.
- Create layouts for assigned analog blocks through floor planning, placement, and routing.
- Perform DRC, ANT, LVS, PERC, EM, and IR verification checks to confirm layout quality.
- Investigate layout tool and process features that can enhance productivity.
- Provide regular status updates, participate in team meetings, and share knowledge with the group.
The must haves:
- Education: Bachelor's degree in Electrical Engineering or a related field.
- Experience: 5+ years of relevant industry experience.
- Custom analog and mixed-signal layout design using deep-submicron CMOS devices, including FinFET transistors.
- Collaboration within an existing team environment and application of a constructive approach to team activities.
- Communication and interpersonal skills applied in collaboration with cross-functional teams.
- Custom layout design of analog and mixed-signal designs, including ADC, DAC, PLL, and SERDES.
- Utilization of industry-standard layout tools, including Cadence Virtuoso, Siemens Calibre, and Ansys Totem, and application of layout design flows for advanced technology nodes.
Nice to haves:
· Scripting using PERL or SKILL.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Originally posted on Himalayas